Field-Programmable Gate Arrays Engineer

The Judge Group; Westminster (CO); On-site; USD 110,000 - 180,000; Full time

Job summary

The Judge Group is seeking an experienced FPGA/SoC engineer to design, implement and verify RTL for payloads, while developing embedded firmware across the stack. You will work on detector interfaces, high-speed data paths, and integration with vendors to ensure on-time deliveries.

A strong RTL background and experience with Versal or similar SoCs are required. You will lead bring-up, validation, and architecture trades, ensuring compliance with safety and performance standards, and you will

Qualifications

• BS/MS in Electrical/Computer Engineering or related field; 5+ years FPGA/firmware experience.
• Experience with AMD Versal, Zynq, or similar adaptive SoCs.
• Strong RTL design in VHDL/Verilog with timing closure.
• Embedded C/C++ on SoC/microcontrollers; bare-metal/RTOS.
• Experience with high-speed interfaces and detectors is a plus.

Responsibilities

• Design, implement, and verify FPGA logic (RTL) for payloads.
• Develop embedded firmware across the payload stack.
• Design and bring up detector-readout and sensor interfaces.
• Implement high-speed data interfaces and processing chains.
• Lead board bring-up and hardware/firmware integration.
• Coordinate with external vendors and ensure on-time delivery.
• Maintain traceability from designs to system requirements.
• Own verification: testbenches, simulations, and hardware-in-the-loop.

Skills

RTL design

Embedded firmware

SoC bring-up

High-speed data interfaces

FPGA verification

VHDL/Verilog

Education

Electrical/Computer Eng degree

Tools

Vivado/Vitis

ModelSim/QuestaSim

Oscilloscope

Logic Analyzer

Schematic reading

Job description

• Design, implement, and verify FPGA logic (RTL) for EOIR and other payloads on AMD Versal adaptive SoC and comparable architectures.
• Develop embedded firmware across the payload stack — Versal processing system, supporting microcontrollers, boot and configuration, and device drivers.
• Design and bring up detector-readout and sensor interfaces (focal-plane arrays / ROICs), including timing, control, and calibration paths.
• Implement high-speed data interfaces and onboard signal- and image-processing chains (SerDes, CameraLink/CoaXPress/MIPI, SpaceWire/SpaceFibre; framing, corrections, compression).
• Lead board bring-up and hardware/firmware integration, debugging at the boundary between hardware and firmware.
• Integrate third-party and vendor IP cores, and coordinate with external developers and vendors to keep payload deliveries on schedule.
• Maintain traceability from FPGA and firmware designs to top-level system requirements, and ensure designs meet applicable safety and performance standards.
• Own verification: testbenches, simulation, timing closure, and hardware-in-the-loop validation.
• Contribute to payload architecture, interface definition, and processor/component selection trades.

Qualifications:

• BS/MS in Electrical Engineering, Computer Engineering, Computer Science, or a related field, plus [5]+ years developing FPGA logic and firmware for payloads, instruments, or other high-reliability embedded systems.

Required Skills:

• Strong RTL design in VHDL or Verilog, with real verification experience and timing closure on AMD/Xilinx toolchains (Vivado/Vitis) and a simulation tool such as ModelSim/QuestaSim.
• Embedded firmware in C/C++ on SoC and microcontroller targets, bare-metal and/or RTOS.
• Direct experience with AMD Versal or Zynq / Zynq UltraScale+-class adaptive SoCs, or a clear path from comparable SoC experience.
• Experience with sensor/detector interfacing and high-speed data interfaces, and with on-FPGA DSP or image-processing chains.
• Hardware and ARM-based SoC bring-up and lab debug: oscilloscope, logic analyzer, protocol analyzers, and schematic reading.
• Must be able to obtain and hold a U.S. security clearance.