Fellow Architect, Pre-Silicon Verification & Validation

Socket.dev; San Jose (CA); On-site; USD 200,000 - 260,000; Full time

Job summary

AMD in San Jose, CA, is seeking a Fellow-level Functional and Performance Verification Architect to lead pre-silicon verification strategy within the Adaptive and Embedded Computing Group (AECG).

You will shape next-generation verification architectures, blending ML/AI innovations with industry standards and leading EDA solutions, driving first-pass silicon success under demanding schedules.

Qualifications

• Expert in programming and scripting languages such as C/C++, Python, Perl, and Ruby, along with strong proficiency in HDL/Verilog and UVM-based verification methodologies.
• Deep background in architecting, developing, and deploying advanced functional verification and validation methodologies, frameworks, and environments for complex semiconductor designs.
• Hands-on experience with pre-silicon prototyping and emulation platforms and their application to functional and performance verification.
• Self-motivated technical leader with a demonstrated ability to identify innovation opportunities, define new methodologies, and drive initiatives from concept through successful deployment.
• Expert understanding of functional and performance verification tools, technologies, and solutions offered by leading EDA vendors. (Synopsys, Cadence Design, Siemens)
• Strong analytical and problem-solving capabilities, with a rigorous attention to detail and a passion for tackling complex technical challenges.
• Proven ability to collaborate effectively across diverse engineering disciplines, organizations, and global teams while delivering high-quality results on schedule.
• Established record of technical thought leadership through publications, technical papers, patents, and presentations at internal and external conferences.

Responsibilities

• Drive the definition, development, and execution of industry-leading functional and performance verification and validation strategies, encompassing verification planning, testbench architecture, development of verification collaterals, debug methodologies, and coverage closure across IP, subsystem, and SoC programs within AECG and AMD.
• Lead the evolution of simulation-based verification methodologies, encompassing constrained-random, directed, and coverage-driven approaches, while advancing formal, power, performance, and implementation verification strategies across the AECG and AMD.
• Lead the advancement of simulation-based verification methodologies—including constrained-random, directed, and coverage-driven techniques—while enhancing formal, power, performance, and implementation verification capabilities across the verification organization.
• Lead the evolution of firmware-based validation strategies and methodologies across prototyping and emulation platforms, accelerating verification convergence and silicon readiness.
• Influence and shape the evolution of verification methodologies by working closely with AECG executives and senior leaders to address the needs of current and future silicon programs.
• Work closely with architecture, design, and verification leaders to identify emerging challenges, align on requirements, and develop scalable verification methodologies that improve quality, efficiency, and predictability across future products.
• Influence architectural and design decisions by partnering with architecture and RTL teams to embed “First-Time-Right” and Design-for-Verification principles into next-generation products.
• Establish and lead strategic engagements with EDA vendors to influence product roadmaps, enhance existing capabilities, and develop next-generation verification methodologies and tools.
• Serve as a technical mentor and trusted advisor to verification engineers across AECG, elevating organizational expertise through coaching, knowledge sharing, and thought leadership.
• Contribute to AMD’s technical leadership and industry presence through publications, technical papers, and presentations at both internal and external conferences.

Skills

C/C++

Python

Perl

Ruby

HDL/Verilog

UVM-based verification

Constrained-random

Formal verification

EDA Tools

Education

B.S., M.S., or Ph.D. in Electrical Engineering, Computer Engineering, Computer Science

Tools

Synopsys

Cadence

Siemens

Job description

AMD in San Jose, CA, is seeking a Fellow-level Functional and Performance Verification Architect to lead pre-silicon verification strategy within the Adaptive and Embedded Computing Group (AECG).

You will shape next-generation verification architectures, blending ML/AI innovations with industry standards and leading EDA solutions, driving first-pass silicon success under demanding schedules.