Experienced FPGA Design Engineer — Verilog & Timing Expert

Intellectt Inc; Raleigh (NC); On-site; USD 110,000 - 160,000; Full time

Job summary

Intellectt Inc. in Raleigh, NC seeks an experienced FPGA Engineer with 5-7 years of hands-on design expertise. You will work on Verilog RTL, timing closure, and clock architecture while using tools like Vivado, Quartus, Libero, and Questa/ModelSim. Bring-up and debugging on FPGA hardware are required.

Applicants should be proficient in CDC, reset design, pipelining, FIFOs, and memory synchronization, contributing to robust, high-performance digital systems.

Qualifications

• 5-7 years of FPGA engineering experience.
• Strong Verilog HDL and RTL design expertise.
• Knowledge of CDC, reset design, pipelining, FIFO/memory, and synchronization.
• Experience with FPGA tools: Vivado, Quartus, Libero, Questa/ModelSim.
• Solid understanding of STA, timing constraints, timing closure and clock architecture.
• Hands-on FPGA hardware bring-up and debugging.

Skills

Verilog RTL design

STA timing analysis

FPGA bring-up & debugging

Clock architecture knowledge

Pipelining & FIFOs

Tools

Vivado

Quartus

Libero

Questa/ModelSim

Job description

Intellectt Inc. in Raleigh, NC seeks an experienced FPGA Engineer with 5-7 years of hands-on design expertise. You will work on Verilog RTL, timing closure, and clock architecture while using tools like Vivado, Quartus, Libero, and Questa/ModelSim. Bring-up and debugging on FPGA hardware are required.

Applicants should be proficient in CDC, reset design, pipelining, FIFOs, and memory synchronization, contributing to robust, high-performance digital systems.