Ethernet Scale-Up Architect & Principal Engineer

TylSemi; San Jose (CA); Hybrid; USD 240,000 - 420,000; Full time

Benefits offered by this job

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Job summary

TYLsemi is seeking a Principal Engineer to architect and lead the Ethernet Scale-Up Networking (ESUN) for AI/HPC interconnects. You will drive architecture, RTL design, verification, and silicon bring-up across cross-functional teams, shaping product strategy and roadmaps.

The role demands 15+ years in ASIC/SoC design, deep SystemVerilog expertise, and a track record delivering high-speed networking silicon for scalable AI systems.

Qualifications

• 15+ years ASIC/SoC architecture and design experience.
• Proven track record delivering high-speed interconnect silicon.
• Deep expertise in SystemVerilog/RTL design and datapath architecture.
• Experience across full ASIC lifecycle from architecture to production.

Responsibilities

• Define architecture for Ethernet-based AI scale-up interconnects and accelerator fabrics.
• Lead development of high-performance Ethernet Subsystem microarchitectures including RDMA, packet processing, network offload, traffic management, congestion control, and reliability mechanisms.
• Drive execution from architecture through RTL, verification, physical design, silicon bring-up, and production.
• Collaborate across hardware, firmware, software, and system teams to deliver industry-leading AI networking solutions.

Skills

ASIC/SoC architecture

RTL design

Ethernet RDMA

Traffic management

Cross-functional leadership

Job description

TYLsemi is seeking a Principal Engineer to architect and lead the Ethernet Scale-Up Networking (ESUN) for AI/HPC interconnects. You will drive architecture, RTL design, verification, and silicon bring-up across cross-functional teams, shaping product strategy and roadmaps.

The role demands 15+ years in ASIC/SoC design, deep SystemVerilog expertise, and a track record delivering high-speed networking silicon for scalable AI systems.