ESD & Latch-Up Reliability Engineer - Tech Development

Intel; Hillsboro (OR); On-site; USD 156,000 - 220,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Retirement plan

Paid time off

Job summary

Intel in Hillsboro, Oregon seeks an Experienced Hire engineer in Technology Development ESD/LU reliability to advance research and development in ESD and latch-up reliability for circuits. You will design test structures, run experiments, and analyze results, contributing to design-rule documentation to support internal and foundry teams.

The role emphasizes ESD characterization with TLP, data-driven analysis, and collaboration with design teams to mitigate failure mechanisms in analog circuits.

Qualifications

• Master's degree in Electrical Engineering, Reliability Engineering, Physics, or related technical field.
• 3+ years experiences in ESD or LU reliability engineering
• 3+ years of experience with Device Physics, device characterization and/or basic VLSI design knowledge

Responsibilities

• Develop and document design rules to improve ESD and latch-up reliability in circuits.
• Design and test test structures, run experiments, analyze data from test structures.
• Perform ESD characterization on test structures using transmission line pulse (TLP).
• Consult design teams to ensure ESD risks are addressed in analog circuits.

Skills

ESD reliability

LU reliability

Device physics

VLSI basics

Education

Master's degree in Electrical Engineering or related field

Tools

TLP measurement

JMP/Excel data analysis

Job description

Intel in Hillsboro, Oregon seeks an Experienced Hire engineer in Technology Development ESD/LU reliability to advance research and development in ESD and latch-up reliability for circuits. You will design test structures, run experiments, and analyze results, contributing to design-rule documentation to support internal and foundry teams.

The role emphasizes ESD characterization with TLP, data-driven analysis, and collaboration with design teams to mitigate failure mechanisms in analog circuits.