Sr. EDA Tools Engineer - PERC ESD

Intel; Hillsboro (OR); On-site; USD 149,600 - 284,580; Full time

Benefits offered by this job

Competitive pay

Stock bonuses

Health benefits

Retirement plans

Vacation time

Job summary

Intel is looking for a skilled engineer in Hillsboro, Oregon, to join the Design Technology Platform. This role focuses on developing ESD/LU rule decks to expedite product market readiness. Candidates must possess a Master's or Ph.D. in Electrical Engineering or Computer Engineering, along with several years of experience in physical design verification.

The right candidate will collaborate with cross-functional teams and drive innovation in verification tooling. Competitive salary and comprehensive benefits are offered.

Qualifications

• 3+ years of experience in physical design verification.
• 2+ years of experience with ESD PERC rule decks/runset development.
• 2+ years of experience in scripting for QA and flow automation.

Responsibilities

• Develop ESD/LU rule decks aligned with design requirements.
• Collaborate with teams to implement new tool features.
• Lead innovation initiatives in verification automation.

Skills

Physical design verification

ESD PERC rule decks development

Scripting (Python, Tcl, Perl)

Analytical problem-solving

Education

Master’s degree or Ph.D. in Electrical Engineering or Computer Engineering

Job description

Job Description

Intel is shaping the future of technology to help create a better future for the entire world. Our work in pushing forward fields such as AI, analytics, and cloud‑to‑edge technology is at the heart of countless innovations. With a career at Intel, you’ll have the opportunity to power major breakthroughs and create enhancements that improve everyday quality of life.

Job Details

The position is within the Design Technology Platform (DTP) organization, specifically the PERC ESD development team. The role focuses on developing PERC ESD rule decks for Intel’s latest technologies, enabling design teams to bring products to market faster and drive PDKs toward industry‑standard methods.

Responsibilities

• Develop ESD/LU rule decks aligned with the ESD Design Rule Manual (DRM) and reliability requirements.
• Create and maintain reliability ESD and LU design rule methodologies and specifications.
• Collaborate with internal design, reliability, and CAD teams as well as external EDA vendors to define and implement new tool features and requirements.
• Build and execute test cases for rule debugging, validation, and sign‑off.
• Define QA requirements and drive related automation to improve robustness and efficiency of rule checks.
• Lead innovation initiatives to enhance existing ESD/LU verification automation, tools, and methodologies.
• Identify and analyze ESD/LU design problems, define root causes, and drive practical solutions across teams.

Qualifications

Minimum qualifications:

• Master’s degree or Ph.D. in Electrical Engineering or Computer Engineering.
• 3+ years of relevant industry experience in physical design verification (reliability, device physics, process technology, and design rules, extraction, or related domains).
• 2+ years of experience with ESD PERC rule decks/runset development and debugging (or equivalent reliability/DRC tools).
• 2+ years of experience in scripting (e.g., Python, Tcl, Perl, or similar) for QA and flow automation.

Preferred qualifications:

• Creative, independent thinker with strong analytical and problem‑solving abilities.
• Strong knowledge of ESD/LU PreSi models (HBM, CDM), I/O design, and related methodologies.
• Strong attention to detail and excellent organization skills.
• Ability to connect the dots across domains and propose cross‑disciplinary optimal solutions.
• Self‑drive with strong leadership skills; able to influence and align internal and external stakeholders.
• Excellent written and verbal communication skills; able to present complex technical concepts clearly and concisely.
• Proven success working with cross‑functional and cross‑site teams, with the ability to influence multiple internal and external partners.
• Demonstrated ability to work in a fast‑paced, team‑oriented environment and drive issues to closure.
• Experience driving cross‑functional and industry‑wide initiatives or task forces.

Benefits

Intel offers a comprehensive benefits package including competitive pay, stock bonuses, health, retirement, vacation, and other programs. For full details, please review Intel Benefits.

Compensation

Annual salary range for U.S. locations: $149,600.00 – $284,580.00 USD.

Work Model and Location

This role requires an on‑site presence at Hillsboro, Oregon. The position is a full‑time, experienced‑hire role.

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation, or ordinance.