Physical Design Engineer

Open Systems Inc.; Austin (TX); On-site; USD 140,000 - 163,000; Full time

Job summary

Open Systems Inc. is seeking a Physical Design Engineer to design and optimize digital blocks for advanced technology nodes. The role focuses on Place & Route (PnR), PPA optimization, and timing convergence from netlist to GDSII.

You will lead floorplanning, placement, CTS, routing, and timing signoff, work with RTL/STA/DFT teams, and ensure tapeout success across Mountain View or Austin locations.

Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Experience with 7nm/5nm/3nm nodes is advantageous.
• Strong debugging and problem-solving skills.

Responsibilities

• Drive block-level physical design from netlist to GDSII.
• Perform floorplanning, power planning, placement, CTS, routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA) targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR (Electromigration & IR Drop) analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
• Debug physical design issues and drive design convergence within project schedules.

Skills

PnR

Floorplanning

Placement

CTS

Routing

Timing Closure

STA

SDC

EMIR

PPA Optimization

Power Optimization

Timing Convergence

Education

Bachelor's or Master's in Electrical/Electronics Engineering

Tools

Cadence Innovus

RedHawk

Voltus

Job description

We are hiring for our client, so please let me know if you are interested in this opportunity!

Job Title: Physical Design Engineer

Location: Mountain View, CA/ Austin, TX

Duration: Full Time

Pay Range: $140k - $163k Depends on the experience.

Job Description

We are looking for a Physical Design Engineer with strong expertise in Place & Route (PnR), Power-Performance-Area (PPA) optimization, and timing convergence for advanced technology nodes.

Key Responsibilities

• Drive block-level physical design implementation from netlist to GDSII.
• Perform floorplanning, power planning, placement, clock tree synthesis (CTS), routing, and physical verification.
• Optimize designs for Power, Performance, and Area (PPA) targets.
• Achieve timing closure across multiple corners and modes.
• Analyze and resolve setup, hold, transition, capacitance, and noise violations.
• Develop and maintain timing constraints (SDC) and STA signoff methodologies.
• Perform EMIR (Electromigration & IR Drop) analysis and closure.
• Collaborate with RTL, DFT, STA, and Signoff teams to ensure successful tapeout.
• Debug physical design issues and drive design convergence within project schedules.

Required Skills

• Strong experience in Physical Design and PnR flow.
• Floorplanning
• Placement & Optimization
• Clock Tree Synthesis (CTS)
• Routing
• Timing Closure
• Static Timing Analysis (STA)
• Timing Constraints (SDC)
• EMIR Analysis
• PPA Optimization
• Experience with industry-standard EDA tools such as:
• Cadence Innovus (optional)
• RedHawk / Voltus (EMIR)
• Good understanding of low-power design techniques and signoff methodologies.

Preferred Qualifications

• Bachelor's or Master's degree in Electrical/Electronics Engineering.
• Experience in advanced nodes (7nm/5nm/3nm preferred).
• Strong debugging and problem-solving skills.
• Experience working with cross-functional silicon teams.