Engineer-Staff

Qualcomm; Austin (TX); On-site; USD 140,000 - 210,000; Full time

Job summary

Qualcomm Technologies, Inc. invites an experienced ASIC design engineer in Austin to drive end-to-end PPA optimization. You will bridge synthesis and physical design, focusing on area, power, and performance. Requires hands-on node experience, strong timing skills, and leadership interaction with senior teams.

Responsibilities cover synthesis QoR, floorplanning, CTS, routing, and multi- clock-domain timing closure, with UPF power strategies and advanced tooling proficiency.

Qualifications

• Experience in physical synthesis, floorplanning, placement, CTS and routing.
• Timing constraints writing for synthesis, STA, and timing closure.
• Hands-on with advanced nodes and multi-patterning challenges.
• Knowledge of low-power design methods and UPF usage.

Responsibilities

• Drive end-to-end PPA optimization across synthesis and PD.
• Balance area, power and performance through QoR and timing closure.
• Lead MCMM timing closure across multi-clock domains.
• Collaborate with senior leadership and cross-functional teams.

Skills

Python/Tcl

AI Usage

Scripting

Version Control

Regression

VLSI/PD concepts

Education

Bachelor's degree in Science/ Engineering

Master's degree in Science/Engineering

PhD in Science/Engineering

Tools

Innovus/ICC2

Fusion Compiler/Genus

PrimeTime/Tempus

Job description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > ASICS Engineering

General Summary:

Experience: 5 to 10 years of hands-on experience in Synthesis, Place and Route (PnR), Physical Design, and Timing/Power Signoff.

Job Role:

• Should have strong understanding and in-depth knowledge of Physical Synthesis, and methodologies, Floorplanning, Placement, Clock Tree Synthesis (CTS), Routing, with leading industry standard tools — able to work across the synthesis-to-PnR boundary to drive end-to-end PPA optimization rather than treat it as a handoff.
• Hands-on experience on advanced technology nodes, including node-specific challenges around double/multi-patterning, pin access, cell legalization, and advanced DRC rules.
• Experience with writing and tuning timing constraints for synthesis, STA, timing closure, and pipelining at different levels for performance optimization — and carrying that intent cleanly through to physical closure.
• Primary focus on driving PPA activities: aggressive area recovery, leakage/dynamic power reduction, and Fmax/performance pushes, balancing trade-offs across synthesis QoR and physical implementation.
• Experience in all aspects of timing closure for multi-clock domain, multi-corner multi-mode (MCMM) designs, both at synthesis and at the physical design stage.
• Should have good understanding of low-power design implementation using UPF, including power gating, multi-voltage domains, and level shifter/isolation cell placement/routing.
• Experience with different power optimization flows/techniques across synthesis and PD — such as clock gating, cell sizing, Vt swapping, and buffer/inverter insertion/optimization.

Minimum Qualifications:

• Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.

Preferred Qualifications:

• Master's degree in Electrical/Electronic Engineering, Computer Engineering, or Computer Science.
• 6+ years of ASIC design, verification, validation, integration, or related work experience.
• 2+ years of experience with architecture and design tools.
• 2+ years of experience with scripting tools and programming languages.
• 2+ years of experience with design verification methods.
• 1+ year of work experience in a role requiring interaction with senior leadership (e.g., Director level and above).

Skill Set:

• Proficiency in Python/Tcl and AI Usage. Familiarity with standard software engineering practices like Version Control, Configuration Management, and Regression.
• Familiar with PnR tools (Innovus/ICC2) and Synthesis tools (Fusion Compiler/Genus), with the ability to move fluidly between both to close PPA.
• Proven hands-on experience on advanced nodes , with awareness of node-specific PPA levers and physical constraints.
• Fair knowledge of Static Timing Analysis (PrimeTime/Tempus), LEC, and Low Power (LP) signoff tools.
• Proficient in VLSI front-end and back-end design steps — Synthesis, QoR optimization, floorplanning, placement, CTS, routing, and Equivalence Checking.
• Strong PPA mindset — comfortable owning power, performance, and area metrics as primary KPIs.
• Knowledge of computer architecture and experience in high-speed, low-power processor design will be a plus.

Qualcomm is an equal opportunity employer. If you are an individual with a disability and need an accommodation during the application/hiring process, rest assured that Qualcomm is committed to providing an accessible process. You may e-mail [e-mail] or call Qualcomm's toll-free number found here. Upon request, Qualcomm will provide reasonable accommodations to support individuals with disabilities to be able participate in the hiring process. Qualcomm is also committed to making our workplace accessible for individuals with disabilities. (Keep in mind that this email address is used to provide reasonable accommodations for individuals with disabilities. We will not respond here to requests for updates on applications or resume inquiries).

EEO Employer: Qualcomm is an equal opportunity employer; all qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or any other protected classification.

Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.

Pay range and Other Compensation & Benefits:

$140,000.00 - $210,000.00

The above pay scale reflects the broad, minimum to maximum, pay scale for this job code for the location for which it has been posted. Even more importantly, please note that salary is only one component of total compensation at Qualcomm. We also offer a competitive annual discretionary bonus program and opportunity for annual RSU grants (employees on sales-incentive plans are not eligible for our annual bonus). In addition, our highly competitive benefits package is designed to support your success at work, at home, and at play. Your recruiter will be happy to discuss all that Qualcomm has to offer – and you can review more details about our US benefits at this link.