Engineer, Silicon Validation

Ayar Labs; San Jose (CA); On-site; USD 135,000 - 160,000; Full time

Job summary

Ayar Labs is seeking a silicon validation engineer in San Jose (on-site) to own the silicon bring up and validation of optical chiplets. You will perform post-silicon bringup and characterization across SerDes, photonic, and mixed-signal blocks, building the test infra and automation to ensure products meet specs before customer deployment.

Ideal candidates have hands-on test experience with high-speed devices, strong lab skills, and a collaborative mindset to work with firmware and design teams

Qualifications

• Bachelor's degree in Electrical Engineering or related field with 1+ years of relevant industry experience.
• Hands-on post-silicon bringup and validation of high-speed SoC or mixed-signal devices.
• Knowledge of SerDes PHY operation and NRZ/PAM-4 signaling.

Responsibilities

• Perform initial power-on and bringup of new silicon tape-outs, including boot sequence validation, clock/power domain verification, and initial functionality tests.
• Characterize high-speed SerDes interfaces, photonic control blocks, and mixed-signal blocks; define and execute test plans at block and chip level.
• Use lab test equipment (BERT, oscilloscope, OSA, signal generators) to characterize SI, eye diagrams, BER, jitter, and optical performance metrics.
• Develop and maintain Python-based test scripts and automation frameworks for regression and characterization testing.
• Investigate silicon anomalies and failures; collaborate with design/firmware to develop fixes.
• Write test plans, validation reports, and signoff docs; communicate findings to cross-functional teams.
• Partner with firmware, analog/mixed-signal, digital, and systems teams across the product cycle.

Skills

Post-silicon bringup

SerDes PHY operation

Python scripting

Lab automation

Git/version control

Test/measurement

Problem solving in lab

Education

Bachelor's degree in Electrical Engineering

Tools

BERT

Oscilloscopes

OSA

Signal Analyzers

Job description

Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models.

Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next‑generation AI scale‑up architectures.

Location: San Jose (on-site)
Ayar Labs is shattering AI data bottlenecks by moving data at the speed of light. As pioneers of co-packaged optics (CPO), we are using light instead of electricity to move data faster, further, and with a fraction of the energy needed to fuel the explosive growth of AI models. Backed by industry giants like NVIDIA, AMD and Intel and manufactured in partnership with the world’s leading semiconductor ecosystem, Ayar Labs’ co-packaged optics solution is key to unleashing next‑generation AI scale‑up architectures.
In this role, you will own the silicon bring up and validation of our optical chiplets. You will execute post-silicon bringup and characterization across SerDes, photonic, and mixed‑signal blocks, building the test infrastructure and automation that ensures our products meet and exceed specification before customer deployment.

Essential Functions

• Perform initial power‑on and bringup of new silicon tape‑outs, including boot sequence validation, clock/power domain verification, and initial functionality tests.
• Perform functional and electrical characterization of high‑speed SerDes interfaces, photonic control blocks, and mixed signal blocks. Define and execute test plans at both block and chip level.
• Use lab test equipment (BERT, oscilloscope/DCA, OSA, signal generators) to characterize signal integrity, eye diagrams, BER, jitter, and optical performance metrics.
• Develop and maintain Python‑based test scripts and automation frameworks for regression and characterization testing.
• Systematically investigate silicon anomalies and failures; collaborate with design and firmware engineers to develop and verify fixes.
• Write clear test plans, validation reports, and signoff documentation; communicate findings to cross‑functional teams.
• Partner with firmware, analog/mixed‑signal, digital, and systems engineering teams across the full product development cycle.

Basic Qualifications

• Bachelor's degree in Electrical Engineering or related field with 1+ years of relevant industry experience.
• Hands‑on experience with post‑silicon bringup and validation of high‑speed SoC or mixed‑signal devices.
• Working knowledge of SerDes PHY operation and characterization, including NRZ and/or PAM‑4 signaling.
• Proficiency with lab equipment used for high‑speed characterization: BERT, oscilloscopes, signal analyzers.
• Proficiency in Python for test scripting and data analysis.
• Strong troubleshooting skills and ability to work independently in a lab environment.
• Proficiency with version control (Git) and software development environments.

Preferred Qualifications

• Experience with photonic device or electro‑optic system characterization and validation.
• Familiarity with optical measurement equipment (OSA, optical power meters, lasers).
• Experience with high‑speed serial standards: Ethernet (100G+), PCIe, OIF CEI.
• Experience with board‑level debug and hardware bring‑up using JTAG or I2C/SPI interfaces.

Salary range: $135,000 - $160,000

Ayar Labs is an Equal Opportunity Employer and is strongly committed to all policies which will afford equal opportunity employment to all qualified persons without regard to age, sex, national origin, race, color, ethnicity, creed, religion, gender identity, sexual orientation, disability, veteran status, or any other characteristic protected by law. It is the policy of Ayar Labs to provide reasonable accommodation when requested by a qualified applicant or employee with a disability, unless such accommodation would cause an undue hardship. Veterans are more than welcome and encouraged to apply.