End-to-End SoC Validation Engineer

HCLTech; Sunnyvale (CA); On-site; USD 78,000 - 148,000; Full time

Benefits offered by this job

Medical insurance

Dental insurance

Vision insurance

Pharmacy benefits

Life insurance

AD&D

Disability insurance

EAP (Employee Assistance Program)

401(k) retirement plan

Paid time off (PTO)

10 paid holidays

Job summary

HCLTech is seeking a talented SOC Validation Engineer to drive end-to-end validation of complex SoC designs across pre-silicon and post-silicon phases. The ideal candidate will have deep expertise in SoC IP subsystems, including Clock, Reset, Ethernet, and I/O, and will develop test strategies and validation plans to root-cause failures from simulation through first silicon.

Responsibilities include creating verification plans for SoC IP subsystems, executing directed and constrained-random

Qualifications

• Experience in end-to-end SoC validation for pre- and post-silicon phases.
• Strong understanding of IP subsystems and interfaces (Clock, Reset, Ethernet, I/O).
• Ability to develop test strategies, run validation plans, and debug failures.

Responsibilities

• Develop verification plans for SoC-level IP subsystems including clocks, resets, Ethernet, and I/O interfaces.
• Create and run directed and constrained-random tests for IP integration and SoC validation.
• Verify CDC, POR, link negotiation, and data-path integrity across domains.
• Develop automated test frameworks for regression and production testing.

Skills

SoC validation

Clock/Reset/IP integration

Python scripting

Test planning

Debugging & RTL debug

Education

B.S./M.S./Ph.D. in Electrical Engineering or related field

Tools

Python

Perl

Tcl

Emulation platforms (Palladium, Veloce, Protium)

FPGA prototyping

Job description

HCLTech is seeking a talented SOC Validation Engineer to drive end-to-end validation of complex SoC designs across pre-silicon and post-silicon phases. The ideal candidate will have deep expertise in SoC IP subsystems, including Clock, Reset, Ethernet, and I/O, and will develop test strategies and validation plans to root-cause failures from simulation through first silicon.

Responsibilities include creating verification plans for SoC IP subsystems, executing directed and constrained-random