Emulation Verification Engineer

AECOM; Beaverton (OR); On-site; USD 90,000 - 130,000; Full time

Job summary

A leading company seeks an Emulation Verification Engineer to join their team in Beaverton. Candidates will engage in innovative product designs and testing for large System on Chips (SoCs), with responsibilities ranging from developing test plans to low power testing on emulation platforms. The role requires collaboration with cross-functional teams and a strong background in verification environments.

Qualifications

• Bachelor's degree + 3 years relevant experience in the industry.
• Experience with RTL to Emulation tool flow.
• Strong skills in SystemVerilog/Verilog and UVM.

Responsibilities

• Develop and apply synthesizable monitors and checkers.
• Prepare and review test plans for verification.
• Collaborate with teams to test large SoCs.

Skills

Analytical skills

Debugging skills

Scripting (Perl/Python/TCL)

Education

Bachelor's degree

Tools

Verilog

SystemVerilog

UVM

Palladium

FPGA flows

Job description

Emulation Verification Engineer

Location: Beaverton, Oregon, United States

Department: Hardware

Summary

Posted: June 5, 2025

Role Number: 200607781

Imagine what you'll do at Apple! We create innovative products, services, and customer experiences. Join our design verification team focusing on emulation environments for large SoCs. Collaborate with Architecture, Design, and Software teams to port designs onto the Palladium platform, develop test plans, and perform verification activities.

Responsibilities:

• Collaborate with cross-functional teams to bring up large SoCs on emulation platforms.
• Develop and apply synthesizable monitors, checkers, and stimuli.
• Prepare and review detailed test plans.
• Perform low power testing on emulation platforms.
• Develop verification code using Verilog/SystemVerilog/UVM.
• Create random stimulus infrastructure using UVM constraints.

Minimum Qualifications:

• Bachelor's degree + 3 years relevant industry experience.

Preferred Qualifications:

• Understanding of RTL to Emulation tool flow.
• Experience with Standard Emulators (Palladium, Veloce, Zebu) or FPGA flows.
• Proven design verification skills.
• Experience with synthesizable SystemVerilog/Verilog and assertions.
• Experience with SystemVerilog verification environments, including C/C++ DPI, UVM.
• Experience in writing and debugging test firmware.
• Scripting experience (Perl/Python/TCL).
• Strong analytical and debugging skills.
• UVM Acceleration experience is a plus.

Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Learn more about your EEO rights here. We consider qualified applicants with criminal histories in accordance with law. In San Francisco, please review the Fair Chance Ordinance. Massachusetts law prohibits requiring lie detector tests as a condition of employment. We are a drug-free workplace and provide reasonable accommodations for applicants with disabilities.