Emulation Engineer

Yoh Services LLC; Santa Clara (CA); On-site; USD 180,000 - 280,000; Full time

Benefits offered by this job

Medical benefits

Health Savings Account (HSA)

Life & Disability Insurance

401K Retirement Savings Plan

Employee Assistance Program (EAP)

Certification and training programs

Job summary

Yoh Services LLC seeks an Emulation Engineer to develop and maintain Cadence Palladium environments for complex ASICs/SoCs in the Bay Area. The role focuses on accelerating pre-silicon validation and enabling hardware/software integration across teams.

You will debug emulation issues, optimize throughput, and develop automation to improve workflows and regression runs. Strong systems knowledge and Linux scripting are essential.

Qualifications

• 5-15 years of ASIC or SoC verification, emulation, or validation experience.
• Hands-on experience with Cadence Palladium (strongly preferred).
• Experience supporting hardware emulation, hardware/software co-verification, or pre-silicon validation.
• Strong understanding of SystemVerilog, UVM, and RTL debug.
• Experience with networking ASICs, Ethernet, PCIe, or high-speed digital designs.
• Proficiency with Linux environments and scripting using Python, Perl, TCL, or Shell.
• BS/MS in Electrical Engineering, Computer Engineering, or related discipline.

Responsibilities

• Develop, configure, and maintain Cadence Palladium emulation environments for complex ASIC and SoC designs.
• Support design bring-up, hardware/software co-validation, and system-level debug on emulation platforms.
• Collaborate with RTL, Design Verification, Architecture, and Software teams to enable pre-silicon validation and accelerate product development.
• Debug emulation compile, runtime, and performance issues while optimizing emulation capacity and throughput.
• Develop automation and scripting to improve emulation workflows, regression execution, and debug efficiency.

Skills

SystemVerilog

UVM

RTL debugging

Education

BS/MS in Electrical Engineering or Computer Engineering

Tools

Cadence Palladium

Job description

Emulation Engineer

Palladium / ASIC / Networking SoC

Overview

This Bay Area startup is developing next-generation Ethernet networking infrastructure optimized for large-scale AI and GPU cluster environments. They are seeking an Emulation Engineer to develop, maintain, and optimize hardware emulation environments for complex networking ASICs and SoCs. This role will focus on accelerating pre-silicon validation, enabling hardware/software integration, and supporting system-level verification using Cadence Palladium.

Responsibilities

• Develop, configure, and maintain Cadence Palladium emulation environments for complex ASIC and SoC designs.
• Support design bring-up, hardware/software co-validation, and system-level debug on emulation platforms.
• Collaborate with RTL, Design Verification, Architecture, and Software teams to enable pre-silicon validation and accelerate product development.
• Debug emulation compile, runtime, and performance issues while optimizing emulation capacity and throughput.
• Develop automation and scripting to improve emulation workflows, regression execution, and debug efficiency.

Requirements

• 5-15 years of ASIC or SoC verification, emulation, or validation experience.
• Hands-on experience with Cadence Palladium (strongly preferred).
• Experience supporting hardware emulation, hardware/software co-verification, or pre-silicon validation.
• Strong understanding of SystemVerilog, UVM, and RTL debug.
• Experience with networking ASICs, Ethernet, PCIe, or high-speed digital designs.
• Proficiency with Linux environments and scripting using Python, Perl, TCL, or Shell.
• BS/MS in Electrical Engineering, Computer Engineering, or related discipline.

Nice to Have

• Experience with networking ASICs, Ethernet switch silicon, NICs, RDMA, RoCE, or AI networking fabrics.
• Experience with additional emulation or prototyping platforms such as ZeBu, Veloce, or FPGA prototyping.
• Exposure to firmware validation, embedded software bring-up, or hardware/software co-design.
• Experience improving emulation infrastructure, automation, or regression frameworks.
• Background from semiconductor, networking, or AI infrastructure companies.

Estimated Min Rate: $180k annually

Estimated Max Rate: $280k annually

What’s In It for You?

• Medical, Prescription, Dental & Vision Benefits (for employees working 20+ hours per week)
• Health Savings Account (HSA) (for employees working 20+ hours per week)
• Life & Disability Insurance (for employees working 20+ hours per week)
• MetLife Voluntary Benefits
• Employee Assistance Program (EAP)
• 401K Retirement Savings Plan
• Direct Deposit & weekly epayroll
• Referral Bonus Programs
• Certification and training opportunities

Note: Any pay ranges displayed are estimations. Actual pay is determined by an applicant's experience, technical expertise, and other qualifications as listed in the job description.

Yoh, a Day & Zimmermann company, is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, or status as a protected veteran.

Visit https://www.yoh.com/applicants-with-disabilities to contact us if you are an individual with a disability and require accommodation in the application process.

For California applicants, qualified applicants with arrest or conviction records will be considered for employment in accordance with the Los Angeles County Fair Chance Ordinance for Employers and the California Fair Chance Act. All of the material job duties described in this posting are job duties for which a criminal history may have a direct, adverse, and negative relationship potentially resulting in the withdrawal of a conditional offer of employment.

It is unlawful in Massachusetts to require or administer a lie detector test as a condition of employment or continued employment. An employer who violates this law shall be subject to criminal penalties and civil liability.