Embedded Software Development Engineer (R&D Engineer 2/3)

Los Alamos National Laboratory; Los Alamos (NM); On-site; USD 106,400 - 206,300; Full time

Benefits offered by this job

Medical and dental insurance

401(k) with match

Flexible schedules

Onsite gym and wellness programs

Job summary

Los Alamos National Laboratory is hiring a skilled FPGA/Embedded Software Development Engineer for its Embedded Systems for Weapons Analysis team. This position supports high-speed data acquisition systems, with responsibilities depending on the role level: R&D Engineer 2 or 3. The ideal candidates should possess hands-on FPGA design experience and proficiency with relevant tools.

Benefits include insurance options, a 401(k) match, tuition assistance, and wellness programs. The location is onsite in Los Alamos, NM.

Qualifications

• Hands-on FPGA design, development, and testing experience.
• Proficient with FPGA tools and debugging methods.
• Solid knowledge of VHDL and/or Verilog for circuit design.

Responsibilities

• Identify and apply digital design methodologies for flight environments.
• Collaborate with engineers to develop and test firmware.
• Act as a technical leader for R&D Engineer 3.

Skills

FPGA design and development

Proficiency with FPGA tools

Knowledge of VHDL/Verilog

Analytical and troubleshooting skills

Communication skills

Education

Bachelor's Degree in Engineering

Master's Degree in Engineering

Tools

Xilinx Vivado

Intel Quartus

MATLAB System Generator

Job description

What You Will Do

At Los Alamos National Laboratory, the Automation, Robotics, and Control Group (E-3) seeks a skilled FPGA/Embedded Software Development Engineer to join the Embedded Systems for Weapons Analysis (ESWA) team. The role supports high‑speed data acquisition systems for flight programs, providing critical data and performance metrics for flight‑tested assets. Depending on the selected candidate’s skills, the position will be filled at either the Embedded Software Development Engineer R&D 2 or R&D 3 level. Additional responsibilities associated with the higher level will be assigned accordingly.

R&D Engineer Responsibilities

R&D Engineer 2 (salary range: $106,400 – $176,000) will identify and apply digital design methodologies suitable for harsh flight environments, and collaborate with engineers and scientists to develop, deploy, and test firmware and software for onboard data processing and analysis.

R&D Engineer 3 (salary range: $122,300 – $206,300) will act as a technical leader, evaluate design variables, make technical decisions, mentor early‑career staff, and continue to refine communications and leadership skills within multidisciplinary teams.

Minimum Job Requirements

• Hands‑on FPGA design, development, and testing experience; familiarity with Xilinx, Altera/Intel, or Lattice platforms.
• Proficiency with FPGA tools such as Xilinx Vivado, XSIM, Intel Quartus, ModelSim, and debugging via logic analyzers, oscilloscopes, or integrated tools.
• Solid knowledge of VHDL and/or Verilog for digital circuit design, simulation, and synthesis.
• Experience designing combinational and sequential logic, state machines, and data‑path architectures.
• Familiarity with common DSP algorithms and high‑speed communication protocols (SPI, I2C, UART, SpaceWire).
• Strong analytical, troubleshooting, and problem‑solving skills.
• Effective teamwork and clear communication in written and verbal formats.

Education and Experience

R&D Engineer 2: Bachelor’s Degree in Engineering (or equivalent) and 4 years of related experience.

R&D Engineer 3: Master’s Degree in Engineering (or equivalent) and 6 years of related experience; a Ph.D. may be preferred.

Desired Qualifications

• Active Q Clearance or equivalent DoD clearance.
• Experience with AMBA, AXI, and APB interfaces.
• Use of MATLAB System Generator for DSP with HDL Coder.
• High‑Level Synthesis (HLS) experience (Xilinx HLS, Intel HLS).
• Experience with high‑performance FPGA families (Xilinx UltraScale+, Intel Stratix).
• Implementation of soft or hard processor cores in FPGAs (e.g., MicroBlaze, Nios II).
• Proficiency with scripting tools (Python, Tcl, Perl) for design automation.
• Advanced verification techniques (SystemVerilog, UVM).
• Knowledge of real‑time operating systems and low‑latency FPGA designs.
• Hands‑on experience with microcontrollers and SoC devices in HW/SW codesign.
• Signal‑integrity best practices from circuit design to PCB layout.
• Experience with industry design tools (Microchip, AMD, Lattice, Intel, Siemens, Synopsys, Aldec).

Work Location

Onsite at Los Alamos, NM. Management retains discretion for other locations.

Position Commitment

One‑year continuous service required during the term of appointment.

Benefits

• Medical (PPO or high deductible), dental, and vision insurance.
• Basic life and disability insurance.
• Paid parental leave.
• 401(k) with 6% match plus 3.5% yearly vesting.
• Tuition assistance and learning opportunities.
• Flexible schedules and paid time off.
• Onsite gym and wellness programs.
• Extensive relocation packages (outside 50 mile radius).

Equal Opportunity

Los Alamos National Laboratory is an equal opportunity employer. All employment decisions are based on qualification and merit, without regard to protected categories such as race, color, national origin, religion, age, sex, gender identity, sexual orientation, disability, or citizenship.