ASIC/FPGA Verification Engineer 5 - UVM

CTS International; El Segundo (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

CTS International in El Segundo, CA is seeking an experienced verification engineer to resolve complex issues on critical programs, lead technical aspects of proposal preparation, and coordinate engineering support throughout the lifecycle of the product.

Candidates should have strong SystemVerilog and UVM skills, experience with constrained-random verification and verification planning, and be able to communicate clearly while delivering maintainable engineering solutions; a Secret Clearance is

Qualifications

• Proven verification experience, not just test writing.
• 7+ years in verification with 2+ UVM experience; 5+ years acceptable if UVM is solid.
• Strong SystemVerilog and UVM expertise.
• Self-checking and constrained-random verification; verification planning.
• Debugging and coverage closure.
• Requires Secret Clearance.

Responsibilities

• Lead technical aspects of proposal preparation.
• Coordinate engineering support across the lifecycle of the product.
• Identify critical performance measures and develop methods to compute them.
• Develop new concepts for future product designs to meet projected requirements.
• Assist with technology insertion and maintain documentation.

Skills

SystemVerilog

UVM

Verification planning

Constrained-random

Debugging

Secret clearance

Education

Bachelor's degree in engineering or related field

ABET accreditation

Master's or PhD in a technical field

Job description

Takes about 3 minutes. No account required.

Position

Overview

Secret Clearance Required to Start.

100% onsite.

Resolves complex issues on critical programs related to architectural approaches, requirements, specifications and design. Leads technical aspect of proposal preparation. Identifies critical performance measures and develops processes for computing them. Leads activities in support of Supplier Management with make/buy recommendations and other technical services. Coordinates engineering support throughout the lifecycle of the product. Develops new concepts for future product designs to meet projected requirements. Recommends and manages technology insertion. Works under consultative direction.

Across all positions, we are looking for engineers who:

• Demonstrate strong digital hardware fundamentals.
• Exercise sound engineering judgment.
• Work independently with minimal oversight.
• Communicate clearly and proactively.
• Produce high-quality technical documentation.
• Take ownership of their work and deliver maintainable engineering solutions.

6+ months — possible extension and possible FTE opportunity.

Requirements

What you'll need

Required Skills

• Engineering-minded verification engineers, not simply engineers who write test cases.
• 7 or more years of verification 2+ UVM experience, though 5+ years is acceptable if UVM experience is solid.
• Strong SystemVerilog and UVM experience
• Self-checking and constrained-random verification; verification planning
• Debugging; coverage closure
• Secret Clearance

Education/experience typically acquired through advanced technical education from an accredited course of study in engineering, computer science, mathematics, physics or chemistry (e.g. Bachelor) and typically 14 or more years' related work experience (e.g. PhD+9 years' related work experience, Master+12 years' related work experience). In the USA, ABET accreditation is the preferred, although not required, accreditation standard.