DTCO Intern: DRAM PPA & Physical Design

Micron Technology, Inc.; Boise (ID); On-site; USD 25,000 - 33,000; Full time

Benefits offered by this job

Medical insurance

Dental plan

Vision plan

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. is seeking a DTCO Intern to gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level.

You will use industry-standard place-and-route tools and AI-enabled automation to implement, benchmark, and optimize designs while developing practical skills in physical design, timing closure, and design analysis. The role collaborates with standard cell library, RTL and physical design teams, analyzes power, performance and area tradeoffs,

Qualifications

• Pursuing a B.S. or M.S. degree in Electrical or Computer Engineering.
• Understanding of VLSI concepts, CMOS, and ASIC physical design flow.
• Experience with scripting languages (Python, Perl, TCL).
• Strong analytical, problem-solving and debugging skills.
• Expected graduation Fall 2025 or later.

Responsibilities

• Implement standard cell logic blocks using physical design tools (floorplanning, placement, CTS, routing).
• Benchmark power, performance and area across libraries and configurations.
• Perform STA, investigate setup/hold timing, support timing closure.
• Execute DRC, LVS, and IR-drop analyses and assist with design issues.
• Leverage AI tools to automate data collection, reporting and workflow optimization for PPA.

Skills

VLSI concepts

CMOS circuits

ASIC flow

Python

Perl

TCL

Debugging

Education

B.S. or M.S. in Electrical Engineering or Computer Engineering

Tools

Synopsys ICC2

Cadence Innovus

PrimeTime

Job description

Micron Technology, Inc. is seeking a DTCO Intern to gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level.

You will use industry-standard place-and-route tools and AI-enabled automation to implement, benchmark, and optimize designs while developing practical skills in physical design, timing closure, and design analysis. The role collaborates with standard cell library, RTL and physical design teams, analyzes power, performance and area tradeoffs,