DRAM Test Structure & Layout Engineering Intern

1000 Micron Technology, Inc.; Boise (ID); On-site; USD 28,000 - 41,000; Full time

Benefits offered by this job

Medical, dental, and vision plans

Paid time off

Equal opportunity employer

Job summary

Micron Technology is seeking a highly motivated Engineering Intern to join the DRAM Build Enablement and Test Structure Engineering team. You will have the outstanding opportunity to contribute to the development, layout, verification, and analysis of semiconductor test structures used to characterize advanced DRAM technologies.

This position offers hands‑on experience with industry‑leading EDA tools, physical build methodologies, composition rule verification, and silicon evaluation techniques

Qualifications

• Currently pursuing a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, Semiconductor Engineering, Physics, or related field.
• Cannot graduate before September 2027.
• Experience with coding or scripting languages such as Python, Tcl, or Perl.
• Strong analytical and problem‑solving skills.
• Good written and verbal communication skills.

Responsibilities

• Contribute to the development and arrangement of semiconductor test structures (TEGs) for advanced DRAM technology nodes.
• Support physical verification activities, including DRC, LVS, and predefined validation.
• Engage in device, process, and test-structure simulation to evaluate build assumptions and correlate with silicon data.
• Develop and analyze test structures for device characterization, process monitoring, and technology qualification.
• Write automation scripts in Python, Tcl, or related languages to improve engineering efficiency.

Skills

Python

Tcl

Perl

Education

Bachelor's or higher in Electrical/Computer/Semiconductor Engineering or Physics

Tools

Cadence Virtuoso

Calibre

Job description

Micron Technology is seeking a highly motivated Engineering Intern to join the DRAM Build Enablement and Test Structure Engineering team. You will have the outstanding opportunity to contribute to the development, layout, verification, and analysis of semiconductor test structures used to characterize advanced DRAM technologies.

This position offers hands‑on experience with industry‑leading EDA tools, physical build methodologies, composition rule verification, and silicon evaluation techniques