DRAM DFT Engineer – Test Flow & Analytics

Micron Technology, Inc.; Boise (ID); On-site; USD 80,000 - 120,000; Full time

Benefits offered by this job

Competitive benefits package including

Medical, dental, and vision plans

Job summary

Micron Technology, Inc. seeks engineers with CMOS circuit knowledge and DRAM experience to advance test flows and defect analysis. You will collaborate in a team to develop strategies for DRAM Design-for-Test (DFT), recognize fail patterns, and improve test efficiency while maintaining quality.

A background in Python/Java/C/C++ and analytical lab work is expected. The role emphasizes innovation in DFT and solving high-visibility DRAM issues, with opportunities to develop supporting software

Qualifications

• Requires a CMOS circuit background and basic programming skills in Python, Java, or C/C++.
• Knowledge of DRAM and statistical analysis is expected.
• Experience with lab work or software profiling/analytics is a plus.

Responsibilities

• Develop new strategies for DRAM DFT with a team approach.
• Develop a new DRAM test flow strategy and improve test time.
• Perform fail pattern recognition and analyze failure data.
• Improve methodologies to reduce test time and enhance quality.
• Provide solutions to high visibility DRAM product issues.
• Create supporting software tools for Engineering Analysis.
• Invent and innovate related to DFT across the DRAM domain.

Skills

CMOS circuit knowledge

Programming in Python/Java/C or C++

DRAM knowledge

Statistics

Lab experience / analytics tooling

Education

Bachelor’s degree in Electrical Engineering, Computer Science, or Electrical and Computer Engineering

Job description

Micron Technology, Inc. seeks engineers with CMOS circuit knowledge and DRAM experience to advance test flows and defect analysis. You will collaborate in a team to develop strategies for DRAM Design-for-Test (DFT), recognize fail patterns, and improve test efficiency while maintaining quality.

A background in Python/Java/C/C++ and analytical lab work is expected. The role emphasizes innovation in DFT and solving high-visibility DRAM issues, with opportunities to develop supporting software