DRAM Design Verification Lead: Innovate & Mentor

Micron; Boise (ID); Sur place; USD 130 000 - 190 000; Plein temps

Résumé du poste

Micron in Boise seeks an MTS Design Verification Engineer to lead DRAM verification strategy, guide engineering teams, and ensure high-quality, scalable memory solutions across products.

You will mentor engineers, collaborate with global teams, drive verification planning, and advance mixed-signal simulation, validation, and signoff for DDR5 and beyond. A strong CMOS background and hands-on tool experience are required.

Qualifications

• Bachelor's degree in Electrical/Computer Engineering or related field.
• 8+ years in DRAM/memory or advanced CMOS verification.
• Hands-on circuit analysis and debug at the transistor level.
• Experience with simulation tools HSPICE, FINESIM, Verilog, SystemVerilog.
• CMOS fundamentals and semiconductor design principles.
• Leadership and cross-functional collaboration across teams.

Responsabilités

• Lead DRAM verification innovation, driving key technical decisions, architecture, and strategy during product execution.
• Collaborate with global teams to define and implement best-known methods for verification and product development.
• Drive verification planning, coverage closure, and silicon debugging for advanced DRAM products.
• Evaluate and implement new tools, methodologies, and flows to improve verification efficiency and quality.
• Mentor engineers and provide technical leadership while contributing expert guidance to senior leadership teams.

Connaissances

Leadership

Problem-solving

Collaboration

Team mentoring

Communication

Python programming

Formation

Bachelor's degree in Electrical Engineering or Computer Engineering

Master's or PhD in Electrical Engineering (preferred)

Outils

HSPICE

FINESIM

Verilog

SystemVerilog

Description du poste

Micron in Boise seeks an MTS Design Verification Engineer to lead DRAM verification strategy, guide engineering teams, and ensure high-quality, scalable memory solutions across products.

You will mentor engineers, collaborate with global teams, drive verification planning, and advance mixed-signal simulation, validation, and signoff for DDR5 and beyond. A strong CMOS background and hands-on tool experience are required.