Director, SoC Design & AI/ML

Global Foundries; Richardson (TX); On-site; USD 191,000 - 332,000; Full time

Job summary

GlobalFoundries in Richardson, TX seeks a Director of Design Engineering to lead complex SoC programs from concept through tape-out and productization. You will drive architectural execution, front-end design methodology, and cross-functional collaboration to deliver differentiated silicon solutions across advanced nodes.

This leadership role requires 15+ years in semiconductor design with 8+ years in engineering management, a proven track record of ASIC/SoC tape-outs, and strong RTL to GDSII

Qualifications

• Bachelor's, Master's, or Ph.D. in Electrical/Computer Engineering or related field.
• 15+ years of semiconductor design experience with increasing leadership responsibility.
• 8+ years engineering management experience including senior technical teams.
• Proven track record of delivering multiple ASIC/SoC tape-outs across advanced nodes.
• Strong hands-on front-end design: RTL, microarchitecture, synthesis, CDC/Lint, DFT.
• Experience with large-scale SoCs, cross-functional collaboration, and customer interactions.

Responsibilities

• Lead design and execution of complex SoC, AI/ML, networking, compute, or edge products.
• Drive front-end development from architecture through RTL, integration, timing, tape-out.
• Establish best-in-class design methodologies and quality metrics.
• Guide decisions on performance, power, area, reliability, and cost.
• Mentor multi-disciplinary teams across geographies and functions.

Skills

RTL design

Timing closure

Synthesis

DFT/Testing

Leadership

Cross-functional

ASIC tape-out

Education

Bachelor's/Master's/PhD in Electrical/Computer Engineering

Job description

GlobalFoundries in Richardson, TX seeks a Director of Design Engineering to lead complex SoC programs from concept through tape-out and productization. You will drive architectural execution, front-end design methodology, and cross-functional collaboration to deliver differentiated silicon solutions across advanced nodes.

This leadership role requires 15+ years in semiconductor design with 8+ years in engineering management, a proven track record of ASIC/SoC tape-outs, and strong RTL to GDSII