Director of Physical Design

Oho Group; San Francisco (CA); Remote; USD 250,000 - 420,000; Full time

Job summary

Oho Group is seeking a Director of Physical Design to lead a team from research to first silicon on advanced nodes, with a focus on block-level and full-chip PD. This hands-on role includes building a team and collaborating across digital design and verification to ensure robust implementations.

Remote-first with occasional travel; Bay Area candidates preferred. 10+ years in ASIC/SoC PD, Cadence Innovus mastery, and strong timing/Power integrity expertise are required.

Qualifications

• 10+ years of hands-on ASIC/SoC physical design experience.
• Expertise with Cadence Innovus and end-to-end physical design flows.
• Strong understanding of timing constraints, STA, CTS and timing closure.
• Experience with power integrity, IR drop, electromigration and physical verification.
• Strong Tcl scripting; Python or Shell experience is beneficial.
• Experience on advanced process nodes (7nm or below).

Responsibilities

• Own block-level physical design from floorplanning and placement through CTS, routing and signoff.
• Drive timing, congestion, power and signal integrity optimisation.
• Execute timing closure, ECOs and physical verification, including DRC/LVS.
• Work closely with synthesis, STA, DFT and chip-level teams to support successful integration.
• Contribute to power integrity analysis, design reviews and tapeout readiness.

Job description

Director of Physical Design – Stealth Startup – Remote

A very well-backed startup are looking for a Director of Physical Design to guide the team through research and concept to first silicon on advanced nodes. A hands-on technical leadership position, you will own block-level and full-chip physical design, build a team and support colleagues across digital design and verification.

Although applicants based in the Bay Area are preferred, they are willing to consider remote work with occasional travel.

Key Responsibilities

• Own block-level physical design from floorplanning and placement through CTS, routing and signoff.


• Drive timing, congestion, power and signal integrity optimisation.


• Execute timing closure, ECOs and physical verification, including DRC/LVS.


• Work closely with synthesis, STA, DFT and chip-level teams to support successful integration.


• Contribute to power integrity analysis, design reviews and tapeout readiness.

Requirements

• 10+ years of hands-on ASIC/SoC physical design experience.


• Strong experience with Cadence Innovus and end-to-end physical design flows.


• Solid understanding of timing constraints, STA, CTS and timing closure.


• Experience with power integrity, IR drop, electromigration and physical verification.


• Strong Tcl scripting skills; Python or Shell experience is beneficial.


• Experience working on advanced process nodes, ideally 7nm or below.

If you have strong physical design expertise and enjoy solving challenging implementation and signoff problems, I’d be keen to hear from you.