Director of Physical Design

Oho Group; San Francisco (CA); Remote; USD 250,000 - 350,000; Full time

Job summary

OHO Group (Lithuania) is seeking a Director of Physical Design for a stealth startup. The role is remote with occasional travel and offers hands-on technical leadership to own block-level and full-chip physical design from concept to silicon.

You will build and lead a team, collaborating with digital design and verification teams. Responsibilities include floorplanning, placement, CTS, routing, signoff, timing closure, DRC/LVS, power integrity, and tapeout readiness.

Qualifications

• 10+ years of hands-on ASIC/SoC physical design experience.
• Strong Cadence Innovus experience and end-to-end physical design flows.
• Solid timing constraints, STA, CTS and timing closure knowledge.
• Experience with power integrity, IR drop, electromigration and physical verification.
• Strong Tcl scripting; Python or Shell handy.
• Experience on advanced process nodes (7nm or below).

Responsibilities

• Own block-level physical design from floorplanning to signoff.
• Drive timing, congestion, power and SI optimisation.
• Execute timing closure, ECOs and physical verification (DRC/LVS).
• Collaborate with synthesis, STA, DFT and chip teams to integrate.
• Contribute to tapeout readiness and power integrity reviews.

Skills

ASIC/SoC PD

Timing closure

Scripting (Tcl)

Power integrity

Tools

Cadence Innovus

End-to-end PD flows

Job description

Director of Physical Design – Stealth Startup – Remote

A very well-backed startup are looking for a Director of Physical Design to guide the team through research and concept to first silicon on advanced nodes. A hands-on technical leadership position, you will own block-level and full-chip physical design, build a team and support colleagues across digital design and verification.

Although applicants based in the Bay Area are preferred, they are willing to consider remote work with occasional travel.

Key Responsibilities

• Own block-level physical design from floorplanning and placement through CTS, routing and signoff.


• Drive timing, congestion, power and signal integrity optimisation.


• Execute timing closure, ECOs and physical verification, including DRC/LVS.


• Work closely with synthesis, STA, DFT and chip-level teams to support successful integration.


• Contribute to power integrity analysis, design reviews and tapeout readiness.

Requirements

• 10+ years of hands-on ASIC/SoC physical design experience.


• Strong experience with Cadence Innovus and end-to-end physical design flows.


• Solid understanding of timing constraints, STA, CTS and timing closure.


• Experience with power integrity, IR drop, electromigration and physical verification.


• Strong Tcl scripting skills; Python or Shell experience is beneficial.


• Experience working on advanced process nodes, ideally 7nm or below.

If you have strong physical design expertise and enjoy solving challenging implementation and signoff problems, I’d be keen to hear from you.