Director of Memory Design

Acceler8; San Francisco (CA); On-site; USD 250,000 - 350,000; Full time

Job summary

Acceler8 Talent partners with a startup designing a cutting-edge 3D-memory‑integrated AI accelerator platform. This role leads the architecture and ownership of a custom memory controller, guiding design from RTL to tapeout and integration.

You will optimize memory-access pipelines, evaluate bandwidth/latency/power tradeoffs, and adapt controller features for advanced DRAM/TSV interfaces while mentoring engineers in a cutting-edge San Francisco environment.

Qualifications

• 15–20 years of memory design experience and hands-on leadership.
• Direct ownership of memory-controller or memory-subsystem RTL.
• Strong ability to make concrete VLSI tradeoffs and debug timing issues.
• Experience with memory interfaces such as HBM/3D memory is a plus.

Responsibilities

• Own custom controller architecture and SystemVerilog RTL from design through SoC integration and tapeout.
• Design memory-access pipelines and low-latency paths; evaluate scheduling, queue depth, and bandwidth/latency/power tradeoffs.
• Adapt controller functions such as scheduling, ECC, refresh, training and power management to interface requirements.
• Optimize DRAM/3D-memory connectivity and TSV interfaces with memory partners.
• Drive lint, CDC/RDC, equivalence, synthesis, constraints and timing convergence with PD and verification teams.
• Define and review verification plans, maintain technical documentation and mentor engineers.

Skills

Memory controller ownership

SystemVerilog RTL design

DDR/LPDDR/GDDR expertise

Memory data-path optimization

VLSI tradeoff analysis

Tapeout experience

CXL / multi-die integration

Job description

Director of Memory Design

Acceler8 Talent is partnering with a startup designing a cutting-edge 3D-memory-integrated AI accelerator platform to hire an experienced, visionary Director of Memory Design.

In this role, you'll architect and implement a custom memory controller. You'll own the access path from memory requests to data delivery, extending an existing controller for custom requirements.

What You'll Do:

• Own custom controller architecture and SystemVerilog RTL from design through SoC integration and tapeout.
• Design memory-access pipelines and low-latency paths; evaluate scheduling, queue depth and bandwidth/latency/power tradeoffs.
• Adapt controller functions such as scheduling, ECC, refresh, training and power management to interface requirements.
• Optimize custom DRAM/3D-memory connectivity, collaborating with memory partners on TSV fabrics and interface requirements.
• Drive lint, CDC/RDC, equivalence, synthesis, constraints and timing convergence with physical-design and verification teams.
• Define/review verification plans, maintain technical documentation and mentor engineers.

What You Bring:

• Direct memory-controller or substantial memory-subsystem architecture and RTL-design ownership.
• Strong DDR/LPDDR/GDDR understanding and deep memory request/data-pipeline reasoning. SystemVerilog, front-end convergence and scripting; multiple successful silicon tapeouts.
• Ability to make concrete VLSI tradeoffs and debug complex timing and structural design issues.
• 15-20 years of relevant experience; hands‑on technical leadership is central.
• HBM2/2E/3 base-die design, custom DRAM interfaces and 3D/TSV integration. C
• ontroller performance modeling, scheduler evaluation and queue-depth analysis.
• AI inference memory patterns, CXL and multi-die/chiplet integration.
• Low-power techniques and high-speed memory-interface DFT.