Digital Layout Design Engineer for Custom ASICs

Apple, Inc.; Beaverton (OR); On-site; USD 120,000 - 180,000; Full time

Job summary

Apple Inc. in Beaverton, Oregon, is seeking a Digital Layout Designer to join a high-visibility SOC design team.

You will design custom digital layouts for deep SubMicron CMOS, review floorplans with circuit designers, and ensure PDV clean layouts using advanced CAD tools. This role requires a bachelor's in a related field, strong layout experience, and knowledge of LVS/DRC/ERC, CALIBRE, Mentor Graphics or Cadence.

Qualifications

• Bachelor's degree in a related field
• Experience in custom layout design of deep SubMicron CMOS circuits
• Proficiency in layout floorplanning and hierarchical layout assembly
• Understanding RC delay, electromigration, self heating and cross capacitance
• Ability to interpret CALIBRE DRC, ERC, LVS reports
• Excellent communication skills and able to work with multi-functional teams
• Knowledge of memory compiler development or layout automation is a plus

Responsibilities

• Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies
• Reviewing and analyzing floorplans and complex circuits with circuit designers
• Running a complete set of layout design verification tools
• Working with the circuit design team to plan, schedule work and negotiate layout tradeoffs
• Interpretation of LVS, DRC, and ERC reports to find fastest completion of layouts
• Exceed engineering specifications and expectations

Skills

layout floorplanning

standard cell planning

RC delay analysis

electromigration awareness

cross-functional teamwork

CALIBRE DRC/ERC/LVS

Mentor Graphics/Cadence

scripting: CSH/Perl/Skill

layout automation

memory compiler knowledge

Education

Bachelor's degree in related field

Tools

Mentor Graphics

Cadence

CALIBRE

Job description

Apple Inc. in Beaverton, Oregon, is seeking a Digital Layout Designer to join a high-visibility SOC design team.

You will design custom digital layouts for deep SubMicron CMOS, review floorplans with circuit designers, and ensure PDV clean layouts using advanced CAD tools. This role requires a bachelor's in a related field, strong layout experience, and knowledge of LVS/DRC/ERC, CALIBRE, Mentor Graphics or Cadence.