Custom ASIC Layout Designer for Deep SubMicron CMOS

Apple, Inc.

Austin (TX)

On-site

USD 120,000 - 190,000

Full time

43 hours ago
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Job summary

Apple, Inc. seeks a Digital Layout Designer to join its silicon design group, crafting complex digital layouts for state-of-the-art ASICs on deep submicron CMOS nodes.

You will collaborate with integration, CAD, circuit and technology engineers to deliver high-quality macro and library designs. You will review floorplans, run layout verification, and work with circuit designers to optimize tradeoffs for performance and area.

Qualifications

  • Bachelor's degree in related field.
  • Experience in custom layout design of deep SubMicron CMOS circuits.
  • Proficient in layout floorplanning and hierarchical layout assembly.

Responsibilities

  • Designing complex custom layout for digital circuits in deep SubMicron CMOS technologies.
  • Reviewing and analyzing floorplans and complex circuits with circuit designers.
  • Running a complete set of layout design verification tools available on megacells completed.
  • Working with the circuit design team to plan, schedule work and negotiate layout tradeoffs as needed.
  • Interpretation of LVS, DRC and ERC report to find the fastest way to complete layouts.
  • Exceed engineering specifications and expectations.
  • Use advanced CAD tools, mask design knowledge to layout corrections and robust physical design representation of circuits.

Skills

Layout floorplanning
Hierarchical layout
Scripting knowledge
RC delay analysis

Education

Bachelor's degree in related field

Tools

Mentor Graphics
Cadence

Job description

Apple, Inc. seeks a Digital Layout Designer to join its silicon design group, crafting complex digital layouts for state-of-the-art ASICs on deep submicron CMOS nodes.

You will collaborate with integration, CAD, circuit and technology engineers to deliver high-quality macro and library designs. You will review floorplans, run layout verification, and work with circuit designers to optimize tradeoffs for performance and area.

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