Custom Digital Layout Engineer — Submicron CMOS

Apple, Inc.; Santa Clara (CA); On-site; USD 82,000 - 124,000; Full time

Benefits offered by this job

Restricted stock units

Relocation assistance

Education reimbursement

Job summary

Apple, Inc. is seeking a Digital Layout Designer to join the silicon design team in Santa Clara. You will deliver PDV clean layouts for advanced ASICs, working with integration, CAD, circuit and technology engineering to translate innovative ideas into silicon.

You will review floorplans, run verification tools, and interact with circuit designers to optimize layouts under tight schedules. Strong communication and experience with CALIBRE/DRC/ERC/LVS are valued.

Qualifications

• A minimum of a bachelor's degree in related field.

Responsibilities

• Design complex custom layout for digital circuits in deep SubMicron CMOS technologies.
• Review floorplans and complex circuits with circuit designers.
• Run complete set of layout verification tools.
• Collaborate with circuit design team to plan and schedule work.
• Interpret LVS, DRC and ERC reports to optimize layouts.
• Meet engineering specs and push for robust design.

Skills

Custom layout

Floorplanning

Cell planning

RC delay analysis

Electromigration

Communication skills

DRC/ERC/LVS interpretation

Layout automation

Memory layout basics

Education

Bachelor's degree in related field

Tools

Mentor Graphics

Cadence layout tools

CSH

PERL

SKILL

Job description

Apple, Inc. is seeking a Digital Layout Designer to join the silicon design team in Santa Clara. You will deliver PDV clean layouts for advanced ASICs, working with integration, CAD, circuit and technology engineering to translate innovative ideas into silicon.

You will review floorplans, run verification tools, and interact with circuit designers to optimize layouts under tight schedules. Strong communication and experience with CALIBRE/DRC/ERC/LVS are valued.