Senior Analog EDA/CAD ASIC Engineer

NOKIA; Sunnyvale (CA); On-site; USD 120,000 - 160,000; Full time

Job summary

NOKIA is seeking a High-Speed Analog EDA/CAD Engineer in Sunnyvale, CA, for a full-time position. This role involves supporting and developing design solutions for high-speed analog ASIC design, working throughout all phases of the tool flow.

The ideal candidates should have a strong background in IC design processes, specifically with analog and mixed-signal ICs, and substantial experience with tools like Cadence Virtuoso and Mentor Calibre. Candidates are expected to thrive in a collaborative environment.

Qualifications

• 5 years of experience as a high-speed analog & mixed-signal IC CAD professional.
• Experience with CMOS and bipolar IC technologies.
• Ability to support EPDA users and solve problems efficiently.

Responsibilities

• Install and customize external vendor PDKs for SiGe and CMOS processes.
• Contribute to design standards and IC development processes.
• Execute layout efforts including archive and tapeout processes.

Skills

Expert in high-speed analog and mixed-signal IC design concepts

Fluent with analog EDA tools, including Cadence Virtuoso

Strong programming skills

UNIX/Linux knowledge

Education

BS in Engineering

MS in Engineering

PhD in Engineering

Tools

Cadence Composer

Mentor Calibre

Job description

High-Speed Analog EDA/CAD Engineer

Full‑time position located in Sunnyvale, CA. Infinera is seeking an EDA/CAD Engineer to support and develop SiGe and CMOS design solutions for the high‑speed analog ASIC design team, including all phases of the tool flow—foundry interface, PDK installation and support, tool evaluation and installation, layout, archive and tapeout.

Responsibilities

• Install, customize and support external vendor PDKs for both SiGe and CMOS processes.
• Install, customize and support a custom IC and RF CAD environment for designing high‑speed (10‑40 Gb/s), broadband, mixed‑signal integrated circuits for fiber‑based wireline applications.
• Lead and contribute to the development of design standards, IC development processes, CAD tools and design flows.
• Execute and support layout efforts, including archive and tapeout processes.

Minimum Expertise Requirements

• Expert in high‑speed analog and mixed‑signal IC design concepts with superior critical thinking, problem‑solving and engineering judgment.
• Fluent with analog EDA front‑end and back‑end tools, including Cadence Virtuoso and ADE.
• Strong Skill programming skills.
• Experience with Mentor Calibre (end‑user support and rule‑deck writing).
• Detailed understanding of advanced high‑speed analog & mixed‑signal layout concepts.
• FlexLM license management knowledge.
• Strong UNIX/Linux knowledge.
• Preferred but not required: Perforce experience, Ocean scripting and advanced modeling and simulation knowledge, and Linux OS support.

Minimum Experience Requirements

• 5 years of experience working as a high‑speed analog & mixed‑signal IC CAD professional.
• Experience with high‑speed IC technologies, including CMOS and bipolar.
• Experience configuring, documenting, and maintaining high‑speed analog IC design flows.
• Experience with transistor‑level IC design and verification software, e.g., Cadence Composer, Cadence Virtuoso, Cadence Spectre, Virtuoso AMS, Mentor Calibre, and the Skill language.
• General understanding of digital physical design flows, e.g., RTL coding, place and route, DRC/LVS verification.
• Work environment: Comfortable in a fast‑paced setting, strong individual contributor, able to work as a member of a small team, and able to support EPDA users and solve problems efficiently.

Education Requirements

• BS 5+ years
• MS 4+ years
• PhD 3+ years

We act inclusively and respect the uniqueness of people. Our employment decisions are made regardless of race, color, national or ethnic origin, religion, gender, sexual orientation, gender identity or expression, age, marital status, disability, protected veteran status or other characteristics protected by law. We are committed to a culture of inclusion built upon our core value of respect.