Digital ASIC Design Engineer - Radiation-Tolerant Readout

Brookhaven National Laboratory; Upton (NY); On-site; USD 85,000 - 120,000; Full time

Job summary

Brookhaven National Laboratory seeks a Digital ASIC Design Engineer to develop advanced readout ASICs and SOC architectures for scientific instrumentation. You will design RTL in SystemVerilog, work with mixed‑signal teams, and drive timing closure for data‑intensive detector systems in a radiation‑tolerant environment.

You will collaborate across projects including EIC detector readout, while also supporting ASICs for other programs in high‑energy and nuclear physics, photon sciences, and

Qualifications

• Bachelor's degree in EE/CE/Applied Physics or closely related field.
• Experience developing synthesizable RTL in SystemVerilog/Verilog for complex ASICs/SOC.
• Familiarity with CAD/EDA tools and multi‑stage design flows.
• Experience with digital architecture, timing constraints, CDC/RDC methods, and low‑power design.
• Ability to collaborate in a multi‑discipline team and handle scheduling challenges.
• Excellent written and verbal communication for reviews and documentation.

Responsibilities

• Architect, microarchitect, implement RTL and integrate digital ASIC blocks.
• Develop specifications based on detector, timing, power, and integration needs.
• Design synthesizable RTL for data formatting, buffering, triggers, and high‑speed interfaces.
• Create reusable IP, register maps, bus interfaces, clock/reset architectures, FIFOs.
• Perform synthesis, STA, CDC/RDC analysis, power estimation, DFT, and P&R.
• Coordinate with physical and analog teams for floorplanning and timing closure.
• Lead verification plans, test benches, and coverage reviews with engineers.
• Support FPGA prototyping, test boards, characterization, and sensor integration.
• Produce technical docs, design reviews, and proposals for new initiatives.
• Commit to safe, ethical work practices and operational excellence.

Skills

SystemVerilog RTL

ASIC design

Synthesis

Timing analysis

FPGA prototyping

Python scripting

Readout electronics

Radiation-tolerant design

Education

Bachelor's degree in electrical engineering, computer engineering, or applied physics

Tools

Cadence

Synopsys

Siemens CAD/EDA

LabVIEW/FPGA tooling

Job description

Brookhaven National Laboratory seeks a Digital ASIC Design Engineer to develop advanced readout ASICs and SOC architectures for scientific instrumentation. You will design RTL in SystemVerilog, work with mixed‑signal teams, and drive timing closure for data‑intensive detector systems in a radiation‑tolerant environment.

You will collaborate across projects including EIC detector readout, while also supporting ASICs for other programs in high‑energy and nuclear physics, photon sciences, and