Senior Integrated Circuit Digital Design Engineer

Anysilicon; Goleta, Northern (CA, KY); Hybrid; USD 120,000 - 190,000; Full time

Job summary

Raytheon Vision Systems in Goleta, CA seeks a Senior Integrated Circuit Digital Design Engineer to advance imaging sensor tech, including ROIC developments and both front-end and back-end digital design. You will collaborate across teams to deliver innovative CMOS-based readout circuits.

The role emphasizes RTL write‑ups, testbenches, and end‑to‑end design flow with opportunities to mentor junior engineers in a fast-paced environment.

Qualifications

• Bachelor's degree in STEM with 5+ years of relevant experience.
• Experience with Cadence Genus, Innovus, and Synopsys toolchains.
• Proficiency in TCL scripting and linting tools.

Responsibilities

• Design Readout Integrated Circuits for imaging systems across CMOS nodes (180nm to 28nm).
• Write RTL using Verilog/SystemVerilog and create testbenches for simulation and verification.
• Perform Synthesis, STA, Place-and-Route, DFT, and LEC.
• Work independently on digital design tasks through all steps of the digital design flow.
• Train and guide junior engineers.

Skills

Front-End RTL

Back-End PnR

Verilog/SystemVerilog

TCL scripting

Teamwork

Education

Bachelor's degree in STEM

Tools

Cadence Genus

Innovius

Synopsys tools

Job description

Senior Integrated Circuit Digital Design Engineer

Job Description:

Raytheon Vision Systems is seeking a Digital Design Engineer to join their team in Goleta, CA. This role involves designing next-generation digital visible and infrared image sensors, contributing to mixed-signal ASIC/ROIC development, and collaborating with cross-functional teams. The ideal candidate will have a strong background in both front-end and back-end digital design, with a focus on innovative Readout Integrated Circuits (ROIC) for imaging systems.

Responsibilities:

• Design innovative Readout Integrated Circuits for imaging systems in various CMOS nodes (180nm to 28nm).
• Write RTL using Verilog & SystemVerilog, and construct testbenches for RTL simulation & verification.
• Perform Synthesis, Static Timing Analysis, Place-and-Route, DFT, and Logical Equivalence Check.
• Work independently on digital design tasks, covering all steps in the digital design flow.
• Train and guide junior engineers.

Qualifications:

• Bachelor's degree in Science, Technology, Engineering, or Mathematics (STEM) with a minimum of 5 years of relevant experience.
• Experience with Digital Design and Signoff tools (e.g., Cadence Genus, Innovius, Synopsys tools).
• Proficiency in TCL scripting and Lint tools.

Skills:

• Front-End Digital Design (RTL writing and verification).
• Back-End Digital Design (Synthesis and Place&Route).
• Excellent communication (written and oral) and teamwork skills.

Find the Right Semiconductor Partner

• ASIC Design Services
• Verification
• Packaging & Wafer
• Semiconductor IP

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