Digital ASIC Designer for Scientific Instrumentation

Brookhaven Science Associates, LLC; Upton (NY); Presencial; USD 85.000 - 120.000; Jornada completa

Descripción de la vacante

Brookhaven National Laboratory seeks a Digital ASIC Design Engineer to craft advanced readout ASICs and SOC architectures for scientific instrumentation within the Instrumentation Division. You will architect, RTL-design, implement, and integrate digital blocks for detector readout, timing distribution, data concentration, and high-speed transmission.

You will collaborate with analog/mixed-signal designers, verification, physical design, firmware, and detector scientists to ensure successful

Formación

• Bachelor's degree in electrical engineering, computer engineering, applied physics, or closely related field.
• Some experience with developing synthesizable RTL in SystemVerilog/Verilog for complex ASICs or SoC designs.
• Familiarity with ASIC design processes and CAD/EDA tools and their interoperability across design, verification, synthesis, timing, and physical implementation.
• Familiarity with digital architecture, clocking and reset strategies, timing constraints, CDC/RDC methodology, power‑aware design.
• Ability to work effectively in a multi-disciplinary, version-controlled design environment and meet technical/schedule challenges.
• Excellent written and oral communication skills for documenting designs and reviews.

Responsabilidades

• Architect, microarchitect, RTL design, and integrate digital ASICs for detector readout and related programs.
• Develop design specifications with scientists and project stakeholders.
• Design and implement synthesizable RTL in SystemVerilog/Verilog for data formatting, buffering, triggers, calibration, and high-speed interfaces.
• Develop reusable digital IP, register maps, clock/reset architectures, and FSMs for ASIC integration.
• Coordinate with verification to define plans, build test benches, and address design issues before tapeout.
• Support FPGA prototyping, lab evaluation, test-board bring-up, and integration with sensors and firmware.

Conocimientos

RTL design in SystemVerilog

SystemVerilog

ASIC design processes

Digital architecture

Collaboration across teams

Communication skills

Educación

Bachelor's degree in electrical/cs-related

Master's or Ph.D. in electrical engineering/related field

Herramientas

Cadence

Synopsys

Siemens

Descripción del empleo

Brookhaven National Laboratory seeks a Digital ASIC Design Engineer to craft advanced readout ASICs and SOC architectures for scientific instrumentation within the Instrumentation Division. You will architect, RTL-design, implement, and integrate digital blocks for detector readout, timing distribution, data concentration, and high-speed transmission.

You will collaborate with analog/mixed-signal designers, verification, physical design, firmware, and detector scientists to ensure successful