Principal ASIC Design Engineer

Fruition Group US; Austin (TX); On-site; USD 180,000 - 260,000; Full time

Job summary

Fruition Group US is seeking a Principal ASIC Design Engineer to own the end-to-end design of advanced ASICs for quantum qubit control and readout. You will architect mixed-signal blocks, lead RTL and IP integration, and drive physical design closure from floorplan to tape-out in a high-performance environment.

You will collaborate daily with physics, firmware, and systems teams to translate qubit requirements into silicon architectures, and you will mentor junior engineers while selecting

Qualifications

• 10+ years of ASIC design experience.
• Tape-out experience at 28nm and below.
• Deep mixed-signal expertise: high-speed DAC/ADC, PLL/DLL.
• RTL design and verification with SystemVerilog/UVM.
• Proven track record owning a chip end-to-end.

Responsibilities

• Architect and lead design of custom mixed-signal ASICs from spec through tape-out and post-silicon validation.
• Own RTL design, analog/mixed-signal IP integration, and physical design closure from floorplan through signoff.
• Define silicon specifications with physics and systems teams, translating qubit drive/readout into ASIC architecture.
• Lead post-silicon bring-up and characterization; own root-cause and ECO process for silicon bugs.
• Select process nodes and foundry partners; manage IP procurement and vendor relationships.
• Mentor junior ASIC engineers and set the technical standard across the silicon team.

Skills

ASIC design

Mixed-signal

SystemVerilog/UVM

Chip ownership

Cross-functional collaboration

Job description

Our client — a world-leading neutral-atom quantum computing company — is building the custom ASICs that make their platform tick: ultra-low-noise DAC/ADC front-ends, high-speed serialisers, and real-time digital control logic operating at the edge of what silicon can do. They need a Principal ASIC Design Engineer to own this work end-to-end.

What you'll do

• Architect and lead design of custom mixed-signal ASICs for quantum qubit control and readout — from block-level specification through tape-out and post-silicon validation.
• Own RTL design (SystemVerilog/VHDL), analog/mixed-signal IP integration, and physical design closure from floorplan through signoff.
• Define silicon specifications in direct collaboration with physics and systems teams, translating qubit drive and readout requirements into ASIC architecture.
• Lead post-silicon bring-up and characterisation; own root-cause and ECO process for silicon bugs.
• Select process nodes and foundry partners; manage IP procurement and vendor relationships.
• Mentor junior ASIC engineers and set the technical standard across the silicon team.

What you bring

• 10+ years of ASIC design experience with demonstrated tape-outs at advanced nodes (28 nm and below).
• Deep mixed-signal expertise: high-speed DAC/ADC (GSPS range), PLL/DLL, precision reference circuits.
• Strong RTL design and verification background: SystemVerilog, UVM, CDC/lint signoff, low-power (UPF).
• Track record of owning a chip from architecture through production — not just contributing to one.
• Excellent cross-functional communication; able to work daily with physicists, firmware engineers, and system architects.