DFT Principial Engineer

Black Rock Groups; Santa Clarita (CA); On-site; USD 110,000 - 145,000; Full time

Benefits offered by this job

Medical

Vision

Dental

Life insurance

Disability insurance

Paid time off

Job summary

Tech Mahindra seeks a DFT Principal Engineer to lead scan insertion, ATPG, and MBIST activities for SOCs in a customer-focused setting. The role requires 8–12 years of experience, hands-on expertise with Tessent/Modus tools, and a track record in defect coverage and test point insertion.

The candidate will work onsite with a customer, interface with design teams, and contribute to advanced DFT flows in a high-performance environment. Equal opportunity employer policies apply.

Qualifications

• 8–12 years of experience in DFT/EE design
• Strong hands-on with scan insertion and ATPG for SOCs
• Experience with MBIST and fault models
• Proficient in Mentor Graphics Tessent and Synopsys/ Cadence tools

Responsibilities

• Perform scan insertion and ATPG for complex SOCs
• Validate MBIST/insertion and fault models across flows
• Utilize Tessent, Modus, and related tools for coverage analysis
• Contribute to FC compiler and GLS validation in Intel-like environments

Skills

Scan insertion

ATPG Validation for SOC

Tools

Mentor Tessent Scan

Tessent TestKompress

Synopsys FC Compiler

Tetramax

VCS

Verdi

Spyglass

Cadence Xcelium

Modus

Tessent

DC (Design Compiler)

Job description

Job Title: DFT Principal engineer

Location: Santa Clara, CA

Onsite/ Remote: Day 1 Onsite at customer location

The pay range for this role is $110k- $145k per annum including any bonuses or variable pay.

• medical
• vision
• dental
• life
• disability insurance
• paid time off (including holidays, parental leave, and sick leave, as required by law)

The exact offer terms will depend on the skill level, educational qualifications, experience, and location of the candidate.

This role is also open for contract: $65/hr - $80/hr

JD:

Position Responsibilities:

• Experience : 8 to 12 yrs
• Experience in Scan Insertion, ATPG, MBIST

Required Skills:

• Scan insertion
• ATPG Validation for SOC.

• Experience with Tessent and Modus for stuck-at and transition (at-speed) fault models, including coverage analysis and test point insertion.
• Experience on SGDFT, Coverage Analysis & Improvement on SCAN, ATPG, Scan insertion(Quick Synth flow using FC), Standalone Scan insertion flow using DC, MBIST insertion
• Good hands-on experience with ATPG GLS(ZD +SDF) simulation debugs
• Working experience on SSN Pattern Retarget & FC/SOC GLS validation
• Tool flows:
• Mentor Graphics Tessent Scan , Tessent TestKompress, and Synopsys tools FC Compiler, Tetramax, VCS,Verdi, Spyglass and Cadence Xcelium tool .
• Experience of working in Intel environment

"Tech Mahindra is an Equal Employment Opportunity employer. We promote and support a diverse workforce at all levels of the company. All qualified applicants will receive consideration for employment without regard to race, religion, color, sex, age, national origin, or disability. All applicants will be evaluated solely based on their ability, competence, and performance of the essential functions of their positions with or without reasonable accommodations. Reasonable accommodations also are available in the hiring process for applicants with disabilities. Candidates can request a reasonable accommodation by contacting the company ADA Coordinator at [e-mail]."