DFT Methodology Engineer

NVIDIA; Santa Clara (CA); On-site; USD 168,000 - 310,500; Full time

Job summary

NVIDIA is seeking a DFT Methodology Engineer in Santa Clara to lead cross-functional DFT design and verification initiatives for next‑generation semiconductor chips. You will own DFT architectures, implement test access mechanisms, and collaborate with RTL, verification, timing, physical design, and software teams.

The role emphasizes mentoring junior engineers, optimizing test strategies, and driving cost-quality trade-offs while aligning with product schedules and silicon bring-up goals.

Qualifications

• Master's degree in Electrical Engineering with proven DFT experience.
• 10+ years hands-on experience in SoC architecture, RTL design, and verification.
• Strong analytical skills for verification and validation of test patterns on large designs.
• Experience with DFT security is a plus.
• Excellent communication and mentoring skills.

Responsibilities

• Own and work with cross-functional teams on state-of-the-art DFT designs.
• Architect, develop, and deploy DFT methods for RTL design, verification, and bring-up.
• Mentor junior engineers on test designs and trade-offs.

Skills

DFT design

RTL design

Verification

Silicon debug

Test access mechanisms

Cross-functional collaboration

Education

Master's degree in Electrical Engineering

Job description

We are now looking for a DFT Methodology Engineer!

Design‑for‑Test Engineering at NVIDIA works on groundbreaking innovations involving crafting creative solutions for DFT architecture, verification and post‑silicon validation on some of the industry's most complex semiconductor chips.

What You’ll Be Doing

• As a member in our team, you will own and work with cross‑functional teams, implementing state‑of‑the‑art designs in test access mechanisms, I1149.1, I1500, I1687, 1838, memory BIST, scan and memory dump and DFX security methodology.
• In addition, you will help architect, develop and deploy DFT methodologies for our next generation products including RTL design, Verification, pattern generation, partnering with teams like timing, physical design, software, bring‑up, production.
• You will also help mentor junior engineers on test designs and trade‑offs including cost and quality.

What We Need To See

• Master’s degree (or equivalent experience) in Electrical Engineering or related field with proven experience in DFT or related domains.
• 10+ years of hands‑on experience in SoC architecture, RTL design, and verification.
• Excellent analytical skills in verification and validation of test patterns and logic on complex and multi‑million gate designs using vendor tools.
• Good exposure to cross‑functional areas including RTL & clocks design, STA, place‑n‑route and power, to ensure we are making the right trade‑offs.
• Experience in Silicon debug and bring‑up on the ATE with an understanding of pattern formats, failure processing, and test program development.
• Knowledge of DFT security and hardware system security is a plus.
• Exceptional written and oral interpersonal skills with the curiosity to work on rare challenges.

The base salary will be determined based on your location, experience, and the pay of employees in similar positions. The base salary range is $168,000 USD - $264,500 USD for Level 4, and $196,000 USD - $310,500 USD for Level 5. You will also be eligible for equity and benefits.

Applications for this job will be accepted at least until July 17, 2026.

NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.