DFT Engineer Intern

Ambarella; United States; On-site; USD 120,000 - 180,000; Full time

Job summary

Ambarella is seeking a qualified engineer in the United States to design DFT logic and support edge AI vision processors.

You will automate DFT flows (Scan, Compression, MBIST), verify DFT logic, and perform timing analysis for DFT modes on large SoCs.

A Master of Science in Electrical/Computer Engineering is required, along with knowledge of Verilog, scripting, DFT fundamentals, and AI‑assisted programming.

Qualifications

• Knowledge of DFT fundamentals.
• Knowledge of Logic design & Static timing analysis.
• Knowledge of Verilog and any scripting language.
• Knowledge of AI assisted programming.

Responsibilities

• Logic Design to support DFT features.
• Automate DFT Flows (Scan, Compression & MBIST) used for complex multi-million gate SoC.
• Verification of DFT Logic and analysis of fault coverage.
• Timing analysis for DFT Modes.

Skills

DFT fundamentals

Logic design

Static timing analysis

Verilog

Scripting language

AI-assisted programming

Education

MSEE in Electrical / Computer Engineering

Job description

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

Position Responsibilities:

• Logic Design to support DFT features
• Automate DFT Flows (Scan, Compression& MBIST) used forcomplex multi-million gate SoC
• Verification of DFT Logic and analysis of fault coverage
• Timing analysis for DFT Modes

Minimum Requirements:

• MSEE in Electrical / Computer Engineering
• Knowledge of DFT fundamentals
• Knowledge of Logic design & Static timing analysis
• Knowledge of Verilog and any scripting language
• Knowledge of AI assisted programming