DFT Engineer

Ambarella; United States; On-site; USD 140,000 - 150,000; Full time

Job summary

Ambarella seeks a DFT Engineer to drive scan and MBIST efforts for complex CV SoCs. You will implement DFT flows from RTL through post-production, using Verilog and Python, and collaborate with product teams to validate patterns on ATE.

The role requires 1–5 years in DFT, knowledge of scan diagnostics, and familiarity with Mentor Tessent. A strong design/ timing background is essential, with base salary in the stated range and RSU incentives.

Qualifications

• Requires MS or BS in Electrical/Computer Engineering with 1–5 years in DFT.
• Strong knowledge of DFT fundamentals.
• Knowledge of logic design and timing.
• Proficiency in Verilog and Python.
• Experience with Mentor Tessent is a plus.
• Experience with scan diagnostics is a plus.

Responsibilities

• Implement DFT (scan, compression, MBIST, LBIST, streaming) from RTL to Post-Production for complex CV SoC.
• Analyze clocking scheme and implement clock control structure for at-speed scan testing.
• Develop high-quality scan and MBIST patterns.
• DFT Verification (including post place-and-route timing simulations).
• Work with Product Engineering team to bring up scan & MBIST patterns on ATE.
• Support silicon production activities including failure diagnosis and test optimization.

Skills

DFT implementation

DFT fundamentals

Verilog

Python

Mentor Tessent

Scan diagnostics

Logic design

Timing

Education

MS in Electrical/Computer Engineering

BS in Electrical/Computer Engineering

Tools

Mentor Tessent

Job description

AI Vision Processors For Edge Applications

Our solutions make cameras smarter by extracting valuable data from high-resolution video streams.

Job Description

Ambarella, a worldwide leader in edge AI semiconductors and software, is on a mission to bring artificial intelligence to all types of everyday devices, for enhanced environmental perception in everything from security cameras to robots to autonomous vehicles.

Position Responsibilities:

• DFT implementation (Scan, Compression, MBIST, LBIST, and Streaming Scan Network) from RTL to Post-Production forcomplex multi-million gate Computer Vision SoC.

• Analyze clocking scheme and implement clock control structure for at-speed scan testing

• Develop/Generate high-quality scan and mbist patterns.

• DFT Verification (including post place-and-route timing simulations).

• Work with Product Engineering team to bring up scan & mbist patterns on ATE.

• Support silicon production activities including failure diagnosis and test optimization.

Minimum Requirements:

• MS in Electrical / Computer Engineering or BS in Electrical/Computer Engineering with 1-5 years of experience in DFT implementation

• Knowledge of DFT fundamentals

• Knowledge of Logic design and timing

• Knowledge of Verilog and Python

• Knowledge of Mentor Tessent tools is a plus

• Knowledge of scan diagnostics is a plus

The base salary range is $140,000- $150,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.