DFT Engineer

Ambarella Inc; California (MO); On-site; USD 140,000 - 150,000; Full time

Benefits offered by this job

RSU grants

Competitive benefits

Job summary

Ambarella Inc. is seeking a DFT engineer to drive scan and MBIST implementation for a multi-million gate computer vision SoC. You will translate RTL to post-production, analyze clocking, and develop high-quality scan patterns.

You will collaborate with Product Engineering to bring up patterns on ATE, support silicon production, and apply Verilog and Python skills to optimize test. A MS or BS in EE/CE with 1–5 years' experience is required.

Qualifications

• Experience in designing and validating DFT for complex SoCs.
• Proficiency with Verilog and Python for test pattern development.
• Knowledge of scan, mbist, and at-speed testing concepts.

Responsibilities

• DFT implementation from RTL to post-production for a large CV SoC.
• Analyze clocking and implement clock control for at-speed scan tests.
• Develop and generate scan/mbist patterns with high quality.
• DFT verification including post place-and-route timing simulations.
• Support bring-up of patterns on ATE with Product Engineering.
• Assist silicon production with failure analysis and test optimization.

Skills

DFT implementation

Clocking analysis

Verilog

Python

Test pattern generation

MBIST/Scan diagnostics

Timing awareness

Education

MS in Electrical Engineering

BS in Electrical/Computer Engineering

Tools

Mentor Tessent

Job description

Ambarella, a worldwide leader in edge AI semiconductors and software, is on a mission to bring artificial intelligence to all types of everyday devices, for enhanced environmental perception in everything from security cameras to robots to autonomous vehicles.

Position Responsibilities:

• DFT implementation (Scan, Compression, MBIST, LBIST, and Streaming Scan Network) from RTL to Post-Production for complex multi-million gate Computer Vision SoC.
• Analyze clocking scheme and implement clock control structure for at-speed scan testing
• Develop/Generate high-quality scan and mbist patterns.
• DFT Verification (including post place-and-route timing simulations).
• Work with Product Engineering team to bring up scan & mbist patterns on ATE.
• Support silicon production activities including failure diagnosis and test optimization.
• MS in Electrical / Computer Engineering or BS in Electrical/Computer Engineering with 1-5 years of experience in DFT implementation
• Knowledge of DFT fundamentals
• Knowledge of Logic design and timing
• Knowledge of Verilog and Python
• Knowledge of Mentor Tessent tools is a plus
• Knowledge of scan diagnostics is a plus

The base salary range is $140,000 - $150,000. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. The successful candidate will have the opportunity to convert to a full-time regular position. We also offer new-hire RSU grants and the opportunity for annual RSU grants, as well as other highly competitive benefits.