DFT Engineer

Riana Technologies; Santa Clara (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Riana Technologies is seeking an experienced DFT Engineer to drive thorough testability for ICs and SoCs. You will apply Siemens Tessent tools for RTL-based DFT, ATPG pattern generation, MBIST integration, and boundary scan.

The role emphasizes debugging fault coverage, clock DFT, and IO test methodologies, requiring strong analytical and problem-solving skills.

Qualifications

• Strong understanding of DFT fundamentals, including controllability and observability.
• Experience debugging and improving fault coverage.
• Experience with industry-standard DFT/ATPG EDA tools.

Responsibilities

• Design for Test (DFT) for ICs and SoCs.
• Debug and improve fault coverage across designs.
• Verify DFT features such as Boundary Scan, MBIST, and clock DFT.
• Work with RTL design and Verilog/SystemVerilog.

Skills

DFT

ATPG

MBIST

Scan

JTAG/IJTAG

RTL

Tools

Siemens Tessent

Job description

We’re looking for an experienced DFT Engineer with strong hands-on expertise in Siemens Tessent, ATPG, MBIST, Scan, JTAG/IJTAG, and RTL. The ideal candidate will have a strong understanding of DFT methodologies and experience debugging and improving fault coverage.

• Design for Test (DFT) Engineer plays a crucial role in ensuring that integrated circuits (ICs) and systems-on-chip (SoCs) can be thoroughly tested for defects, reliability, and performance.
• Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite.
• Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing.
• Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improvement.
• Experience with MBIST (Memory Built-In Self-Test), including memory test architecture, implementation, and diagnostics.
• Good knowledge of IO Test methodologies for interface and pin-level validation.
• Strong understanding of Clock DFT and clock verification concepts.
• Solid foundation in Digital Design and RTL (Verilog/System Verilog).
• Experience with industry-standard DFT/ATPG EDA tools.
• Experience in verification of DFT features, including Boundary Scan (JTAG), IJTAG, MBIST, High-Speed Scan Testing, and other DFT methodologies.
• Excellent analytical, debugging, and problem-solving skills.