DFT Engineer

Broadcom; San Jose (CA); On-site; USD 122,000 - 195,000; Full time

Benefits offered by this job

Discretionary annual bonus

Equity grant

Annual equity awards

Job summary

Broadcom’s Core Switching Group in San Jose, CA is seeking a DFT engineer to advance DFT ATPG, MBIST pattern generation, and yield optimization across the product portfolio. You will debug patterns, support post-silicon activities, and partner with cross-functional teams.

The role requires deep CMOS device physics knowledge, experience with DFT tools (Tessent), and strong data analytics. This is a full‑time, on‑site position at our R&D center.

Qualifications

• Experience with DFT ATPG/MBIST pattern generation, bring-up and debug.
• Post-silicon pattern conversion; test pattern verification and repair support.
• Strong data analytics and automation knowledge for yield improvement.

Responsibilities

• DFT Pattern post-silicon support: ATPG and MBIST DFT patterns generation, bringup and debug.
• Yield Enhancement: Monitor wafer sort and final test yield, drive continuous improvement.
• Root Cause Analysis: Perform scan diagnostic, mbist and repair debug to pinpoint defects.
• Failure Analysis support for ATPG scan diag and electrical fault isolation.
• NPI & Silicon Bring-Up: collaborate with Global Operations on silicon evaluation and baseline yield.
• Cross functional: work with Product and Test Engineers.
• Data Analytics & Automation: build dashboards, wafer maps, and yield models.

Skills

DFT

ATPG

MBIST

bscan

IJTAG

Pattern debugging

Data analytics

Scripting

Education

Bachelor's degree + experience

Tools

Tessent

Job description

USA-CA San Jose Innovation Drive

Full time

R026964

Job Description:

Broadcom’s Core Switching Group division is seeking a candidate for a DFT engineer. Products include networking switches for Scale up and Scale Out for traditional and AI data centers. This position is at our R&D center in San Jose, CA. The successful candidate will have hands‑on experience for DFT ATPG and mbist pattern debug and drive defect reduction, optimize wafer sort & final test, and maximize yield across our product portfolio.

Responsibilities

• DFT Pattern post-silicon support: ATPG and MBIST DFT patterns generation, bringup and debug

• Yield Enhancement: Monitor wafer sort (CP) and final test (FT) yield, binning distribution, and parametric data. Drive continuous improvement plans to achieve aggressive yield and cost targets.

• Root Cause Analysis: Perform scan diagnostic, mbist and repair debug, resolve yield excursions. Correlate electrical failures to inline fab metrology, defect density, and process tool data.

• Failure Analysis (FA): Support ATPG scan diag and guide physical failure analysis and electrical fault isolation to pinpoint defect mechanisms and process vulnerabilities.

• NPI & Silicon Bring-Up: Partner with the Global Operation team during early silicon evaluation to debug test programs, validate design-for-test (DFT) structures, and establish baseline yield limits.

• Cross functional: Work closely with Product Engineers and Test Engineers

• Data Analytics & Automation: Use AI tools to build automated dashboards, spatial wafer maps, and yield correlation models that proactively flag process shifts.

Requirements

• Deep understanding of CMOS device physics, semiconductor manufacturing processes (Lithography, Etch, Deposition, CMP, Implant), and electrical testing methodologies.

• Knowledge of Testability techniques and features (SCAN, MBIST, bscan.) covering digital logic domain, embedded memories and PHY/IO’s

• Scan flow development, ATPG pattern generation, verification and coverage analysis

• Experience working with Mentor/Siemens DFT Tessent tool for scan/MBIST/bscan/IJTAG pattern generation and debug

• Post Silicon experience in Pattern conversion for Testers, Pattern Bring-up & Debug, Silicon Characterization etc.

• Strong Pre/Post Silicon debugging, analytical and independent problem solving ability.

• Ability to perform volume data analysis, Correlate failures with system failures, Proficiency with Data analysis softwares/languages

• Must be a self-driven engineer with good project management and organizational skills to deliver high quality output in a timely manner.

• Strong scripting, experience with AI tools for quick script development is a plus

Education

• Bachelor's Degree and 8+ years of related experience, or Master's Degree and 6+ years of related experience

Compensation and Benefits

The annual base salary range for this position is USD 121,900.00 To USD 195,000.00

As a valued member of our team, you'll be eligible for a discretionary annual bonus and the opportunity to receive not only a competitive new hire equity grant, but also annual equity awards, connecting your success directly to the company's growth. All subject to relevant plan documents and award agreements.

Broadcom offers a competitive and comprehensive benefits package: Medical, dental and vision plans, 401(K) participation including company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company paid holidays, paid sick leave and vacation time. The company follows all applicable laws for Paid Family Leave and other leaves of absence.

Broadcom is proud to be an equal opportunity employer. We will consider qualified applicants without regard to race, color, creed, religion, sex, sexual orientation, national origin, citizenship, disability status, medical condition, pregnancy, protected veteran status or any other characteristic protected by federal, state, or local law. We will also consider qualified applicants with arrest and conviction records consistent with local law.

If you are located outside USA, please be sure to fill out a home address as this will be used for future correspondence.

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