DFT Engineer

Mirafra Technologies; San Jose (CA); On-site; USD 150,000 - 190,000; Full time

Job summary

Mirafra Technologies is seeking an experienced DFT engineer to design and implement robust testability solutions for large multi-gate, multi-clock-domain SoCs. You will lead ATPG/SCAN/JTAG debugging across blocks and chips, integrate RTL simulations, and leverage Synopsys tools for manufacturing test.

Collaborative work across cross‑functional teams is essential to deliver high-quality silicon. The role requires hands-on DFT experience, strong problem-solving abilities, and a proactive,

Qualifications

• B.Tech / M.Tech (preferred) with 8-15 years of experience in DFT.
• Strong knowledge of DFT architecture, methodologies and structural debug concepts : JTAG.
• Experience in handling DFT of the large multi multimillion gate multi clock domain SoCs.
• Hands on experience in SCAN, ATPG and JTAG implementation at block and chip level.
• Knowledge of Verilog RTL and hands on experience in using simulators and waveform debugging tools.
• Hands on experience in using Synopsys DFT tools like Testmax, Tetramax, DC & FC.
• Experience in post silicon debug.
• Knowledge of Python, Shell scripting, Makefiles, TCL.
• Excellent problem solving skills and highly self-motivated.

Responsibilities

• Design and implement DFT solutions for large multi-gate, multi-clock-domain SoCs.
• Lead and perform ATPG/SCAN/JTAG debugging across blocks and entire chips.
• Integrate DFT flows with Verilog RTL simulations and waveform analysis.
• Utilize Synopsys DFT tools (Testmax, Tetramax, DC, FC) for manufacturing test.
• Debug post-silicon issues and collaborate with cross-functional teams.

Skills

DFT

JTAG

ATPG

SCAN

Verilog RTL

Debugging tools

Waveforms

Python

Shell scripting

Education

B.Tech / M.Tech in relevant field

Tools

Testmax

Tetramax

DC

FC

VCS

Verdi

Job description

• B.Tech / M.Tech (preferred) with 8-15 years of experience in DFT
• Strong knowledge of DFT architecture, methodologies and structural debug concepts : JTAG,
• Experience in handling DFT of the large multi multimillion gate multi clock domain SoCs
• Hands on experience in SCAN, ATPG and JTAG implementation at block and chip level
• Knowledge of Verilog RTL and hands on experience in using simulators and waveform
• debugging tools such as VCS and Verdi
• Hands on experience in using Synopsys DFT tools like Testmax, Tetramax, DC & FC
• Experience in post silicon debug
• Knowledge of Python, , Shell scripting, Makefiles, TCL
• Excellent problem solving skills and highly self-motivated.