DFT Engineer

Highbrow Technology Inc; San Jose (CA); On-site; USD 120,000 - 180,000; Full time

Job summary

Highbrow Technology Inc in San Jose, CA is seeking a DFT/IC test engineer onsite. You will work on hierarchical DFT architecture, scan insertion, ATPG, MBIST and pre/post-layout simulation to boost test coverage and reliability.

Requirements include 3–5+ years in the field, a BS or higher in EE/CE, and programming in Tcl and Perl. Knowledge of JTAG for board-level testing, test clock strategies, timing constraints, and flow development is a plus.

Qualifications

• 3–5+ years industry experience in DFT/test environments.
• BS or higher in EE or CE.
• Proficient in Tcl and Perl programming.
• Experience with JTAG on board-level testing is preferred.

Responsibilities

• Involvement in flow development is a plus.
• Work on hierarchical DFT architecture, scan insertion, ATPG and MBIST.
• Work with test clock strategies and timing constraints for various modes.

Skills

Hierarchical DFT Architecture

Scan Insertion

ATPG

MBIST

DFT Architecture

Test Clock Strategy

Timing Constraints

JTAG

Tcl

Perl

Flow Development

Education

BS in Electrical Engineering or Computer Engineering

Job description

location San Jose CA (Onsite 5 Days/Week)

Experience with Hierarchical DFT Architecture

Experience in Scan Insertion, test Muxing, ATPG, MBist & pre/post-layout simulation

Expertise in Top Level DFT switching with DFT Architecture experience will add value

Expertise in test clock strategy & muxing required

Expertise in test timing constraints for shift, capture, mbist or any special mode & timing closure for

these modes

Familiar with low power testability, state tables, and components (LS, ISO, RET)

Familiar with JTAG for board level interconnect testing

Programming experience in Tcl & Perl is must

Involvement in flow development is a plus

3-5+ years industry experience required

Skill Set: BS or above in electrical engineering or computer engineering