Design Verification Engineering Intern - MS/PhD

Texas Instruments; Bouchard (TX); In loco; USD 34.000 - 48.000; Tempo pieno

Descrizione del lavoro

Texas Instruments is seeking a Design Verification intern to join our DV team in Texas. You will develop verification plans and work with design and system teams to ensure pre-silicon success, build test benches, tests and simulations for DUT behavior, and drive coverage of mixed-signal circuits.

You will run regression tests, track verification status, and use scripting and regression tools to streamline case submission, while contributing to DV strategy, flows, and methodology improvements.

Competenze

• Develop verification plans with design and system teams.
• Create test benches, tests and simulations for DUT behavior.
• Run coverage regressions for SystemVerilog functional coverage.
• Track verification status and communicate issues clearly.
• Use regression tools and scripts to submit cases for analysis.
• Verify chip-level timing between analog and digital circuits (RTL & Gates+SDF).
• Develop constrained-random stimulus and auto-checking environments.
• Contribute to DV strategy, tools, methods, and flows.

Mansioni

• Develop verification plans with design and system teams.
• Build and run test benches and simulations for DUT behavior.
• Work toward defined coverage goals for mixed-signal circuits.

Conoscenze

Verification plans

Test benches

Simulations

SystemVerilog coverage

Regression tooling

Scripting for regression

RTL & Gates+SDF

Constrained-random stimulus

DV strategy & flows

Status tracking & communication

Strumenti

SystemVerilog

RTL

Gates+SDF

Regression tooling

Scripting languages

Descrizione del lavoro

We can't predict what the future holds, but we know Texas Instruments will have a part in shaping it.

As a Design Verification intern in this group, you will be responsible for:

• Developing detailed verification plans while working closely with the design and system team to ensure pre- silicon verification success
• Developing test benches, tests and simulations to DUT behavior
• Running coverage regressions to meet the defined coverage goals for SystemVerilog functional coverage models of mixed-signal circuits for voltages and currents, real numbers, integers, and traditional digital functional coverage.
• Tracking and communicating verification status, issues, and concerns
• Work with regression tools and develop scripts to submit cases for regression analysis
• Utilize RTL and Gates+SDF, including verifying chip-level timing between analog and digital circuits.
• Constrained-random stimulus and auto-checking verification environments, especially constrained-random analog stimulus.
• Contribute to continuous improvements for quality and efficiency on DV strategy, tools, methods and flows

Put your talent to work with us as a Design Engineer Intern - change the world, love your job!