Design Verification Intern: Build Chip Validation

Texas Instruments

Bouchard (TX)

On-site

USD 34,000 - 48,000

Full time

14 days+

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Job summary

Texas Instruments is seeking a Design Verification intern to join our DV team in Texas. You will develop verification plans and work with design and system teams to ensure pre-silicon success, build test benches, tests and simulations for DUT behavior, and drive coverage of mixed-signal circuits.

You will run regression tests, track verification status, and use scripting and regression tools to streamline case submission, while contributing to DV strategy, flows, and methodology improvements.

Qualifications

  • Develop verification plans with design and system teams.
  • Create test benches, tests and simulations for DUT behavior.
  • Run coverage regressions for SystemVerilog functional coverage.
  • Track verification status and communicate issues clearly.
  • Use regression tools and scripts to submit cases for analysis.
  • Verify chip-level timing between analog and digital circuits (RTL & Gates+SDF).
  • Develop constrained-random stimulus and auto-checking environments.
  • Contribute to DV strategy, tools, methods, and flows.

Responsibilities

  • Develop verification plans with design and system teams.
  • Build and run test benches and simulations for DUT behavior.
  • Work toward defined coverage goals for mixed-signal circuits.

Skills

Verification plans
Test benches
Simulations
SystemVerilog coverage
Regression tooling
Scripting for regression
RTL & Gates+SDF
Constrained-random stimulus
DV strategy & flows
Status tracking & communication

Tools

SystemVerilog
RTL
Gates+SDF
Regression tooling
Scripting languages

Job description

Texas Instruments is seeking a Design Verification intern to join our DV team in Texas. You will develop verification plans and work with design and system teams to ensure pre-silicon success, build test benches, tests and simulations for DUT behavior, and drive coverage of mixed-signal circuits.

You will run regression tests, track verification status, and use scripting and regression tools to streamline case submission, while contributing to DV strategy, flows, and methodology improvements.

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