Enable job alerts via email!

Design Verification Engineer, Senior Staff

d-Matrix

Santa Clara (CA)

Hybrid

USD 150,000 - 200,000

Full time

Yesterday
Be an early applicant

Boost your interview chances

Create a job specific, tailored resume for higher success rate.

Job summary

A leading company in generative AI seeks a Design Verification Engineer, Staff to innovate software and hardware solutions. The role offers a unique chance to lead in a fast-paced environment, focusing on cutting-edge technology. Candidates will work collaboratively within an inclusive culture while impacting the technology landscape globally.

Qualifications

  • 15+ years of industry experience or MS with 12+ years.
  • Experience in SoC verification cycle.
  • Hands-on ASIC-SoC design verification experience.

Responsibilities

  • Work on a highly programmable in-memory computing architecture.
  • Contribute to a culture of learning and inclusiveness.
  • Lead verification environments and tape out efforts.

Skills

Verification methodologies (UVM/OVM)
Problem-solving
Fluency with SystemVerilog
Passion for AI

Education

BS in Electrical Engineering
MS in Electrical Engineering

Tools

SystemVerilog
C/C++
SystemC

Job description

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible.Our culture is one of respect and collaboration.

We value humility and believe in direct communication.Our team is inclusive, and our differing perspectives allow for better solutions.We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.

Location:

Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week.

The role: Design Verification Engineer, Staff

What you will do:

We want to build a company and a culture that sustains the tests of time. We offer the candidate a very unique opportunity to express themselves and become a future leader in an industry that will have a huge influence globally. We are striving to build a culture of transparency, inclusiveness and intellectual honesty while ensuring all our team members are always learning and having fun on the journey. We have built the industry’s first highly programmable in-memory computing architecture that applies to a broad class of applications from cloud to edge. The candidate will get to work on a path breaking architecture with a highly experienced team that knows what it takes to build a successful business.

What you will bring:

Minimum:

  • BS in Electrical Engineering, Computer Science or related field with 15+ years of Industry experience or MS Electrical Engineering, Computer Science or related field preferred with 12+ years industry experience.

  • Experience in SoC verification cycle from architecture to tape out to bring up.

  • Good knowledge of verification methodologies such as UVM/OVM etc.

  • Hands on ASIC-SoC Design verification tests and debug experience.

  • Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.

  • Good problem-solving skills, and the passion to take on challenges (particularly in AI domain).

  • Good experience with SystemVerilog, and verification methodology (UVM/OVM/VMM).

  • Passionate about AI and thriving in a fast-paced and dynamic startup culture.

Preferred:

  • Experience with C/C++, SystemC (a big plus!)

  • Successfully lead creation/implementation of multiple SoC verification environments and tape out efforts.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

Get your free, confidential resume review.
or drag and drop a PDF, DOC, DOCX, ODT, or PAGES file up to 5MB.

Similar jobs

Design Verification Engineer, Senior Staff

Marvell Semiconductor, Inc.

Santa Clara null

On-site

On-site

USD 124,000 - 187,000

Full time

26 days ago

ASIC Design Verification Engineer (all levels)

SQL Pager LLC

San Francisco,Sunnyvale null

On-site

On-site

USD 120,000 - 180,000

Full time

8 days ago

Design Verification Engineer, Senior Staff

d-Matrix

Santa Clara null

Hybrid

Hybrid

USD 150,000 - 200,000

Full time

30+ days ago

SoC Verification - Senior Staff Engineer

Synopsys, Inc.

Sunnyvale null

On-site

On-site

USD 120,000 - 160,000

Full time

3 days ago
Be an early applicant

System Verification & Validation Engineer, Platform Safety Assurance

Zoox

Foster City null

On-site

On-site

USD 166,000 - 227,000

Full time

Today
Be an early applicant

Senior Staff Engineer, Design Verification

Samsung Semiconductor

San Jose null

On-site

On-site

USD 180,000 - 290,000

Full time

30+ days ago