Senior Design Verification Engineer

Anysilicon; Needham, Northern (MA, KY); Hybrid; USD 120,000 - 180,000; Full time

Job summary

HPR is seeking a Senior Design Verification Engineer to enhance our high-performance digital infrastructure used in electronic trading. You will verify FPGA compute and networking systems, own the verification lifecycle from spec to coverage, and work with designers to implement robust test plans.

The role requires SystemVerilog expertise, advanced verification techniques, and experience with simulation tools in a Linux environment.

Qualifications

• BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related field.
• 5+ years of experience in design verification for FPGAs or ASICs.
• Proficiency in SystemVerilog for verification.
• Familiarity with advanced verification methods like constrained randomization and functional coverage.
• Experience with simulation and debugging tools (e.g., VCS, Verdi).
• Comfortable working in a Linux environment.
• Strong problem-solving, debugging, and communication skills.

Responsibilities

• Verify and maintain high-performance FPGA compute and networking systems for electronic trading.
• Own the verification process from specification to coverage closure.
• Collaborate with design engineers to execute comprehensive test plans.
• Create and maintain reusable verification components and testbenches in SystemVerilog.
• Lead and mentor junior engineers, fostering a culture of continuous learning.
• Contribute to the improvement of verification processes, tools, and methodologies.

Skills

SystemVerilog

FPGA verification

Linux

Constrained randomization

Functional coverage

Python scripting

Education

BS/MS in Computer/Electrical Engineering or related field

Tools

VCS

Verdi

Job description

HPR is a leading provider of high-performance electronic trading and capital markets infrastructure solutions. We are seeking a Senior Design Verification Engineer to enhance our innovative technology used by tier-1 financial institutions.

Responsibilities:

• Verify and maintain high-performance FPGA compute and networking systems for electronic trading.
• Own the verification process from specification to coverage closure.
• Collaborate with design engineers to execute comprehensive test plans.
• Create and maintain reusable verification components and testbenches in SystemVerilog.
• Lead and mentor junior engineers, fostering a culture of continuous learning.
• Contribute to the improvement of verification processes, tools, and methodologies.

Qualifications:

• BS/MS in Computer Engineering, Electrical Engineering, Computer Science, or related field.
• 5+ years of experience in design verification for FPGAs or ASICs.
• Proficiency in SystemVerilog for verification.
• Familiarity with advanced verification methods like constrained randomization and functional coverage.
• Experience with simulation and debugging tools (e.g., VCS, Verdi).
• Comfortable working in a Linux environment.
• Strong problem-solving, debugging, and communication skills.

Skills:

• Deep understanding of computer architecture and digital design concepts.
• In-depth knowledge of networking protocols (IP, TCP, UDP).
• Experience with high-speed interfaces (PCIe, Ethernet, DDR).
• Familiarity with C programming and scripting in Python and/or Perl.