Design Verification Engineer - SoC

The Consensus; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Medical, dental, and vision packages

Daily lunch + dinner in office

Wellness benefits

Unlimited compute budget

Job summary

Etched is seeking a Design Verification Engineer to join the Systems/Performance Verification team, validating custom IPs powering our silicon. You will verify performance features, develop test infrastructure, and collaborate across RTL, software, and emulation groups to ensure silicon-ready designs.

You will build and maintain performance models, write SystemVerilog and Python tests, and drive end-to-end verification and tuning across the hardware-software stack.

Qualifications

• Strong understanding of digital design, RTL, and ASIC design flows.
• Hands-on performance verification, simulation, and modeling.
• Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog.
• Skilled in writing Python scripts for automation, data analysis, and performance modeling.
• Experience building and maintaining performance models for chip subsystems.

Responsibilities

• Verify performance features against models pre- and post-silicon.
• Collaborate with software and SW/FW/emulation teams to identify performance bottlenecks.
• Develop test plans and infrastructure/tools for performance tuning and verification.
• Improve and maintain architectural performance models.
• Develop SystemVerilog or Python-based tests and checkers to validate RTL and models.
• Develop coverage monitors and analyze coverage to ensure feature completeness.
• Debug performance issues and conduct silicon tuning.
• Drive end-to-end performance tuning across the ASIC design lifecycle.

Skills

SystemVerilog

RTL design

Performance verification

Python scripting

Testbench development

Debugging hardware

Tools

Simulation tools

Job description

About Etched

Etched is building hardware for frontier intelligence. We co-design chips, racks, software, and manufacturing to deliver best-in-class throughput and latency across both prefill and decode workloads. Our first products are heavily focused on inference. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history.

Job Summary

We are seeking a Design Verification Engineer to join our Systems/Performance Verification team. You will ensure the custom IPs powering our chips - including systolic arrays, DMA engines, and NoCs - are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack.

Key responsibilities

• Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon).

• Work closely with software and application developers on identifying performance bottlenecks and tuning the software.

• Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification.

• Improve and maintain the architectural performance models.

• Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model.

• Develop SystemVerilog or Python-based checkers for verifying the performance features.

• Develop coverage monitors and analyze coverage to ensure all performance features are covered.

• Debug performance issues and conduct performance tuning on silicon.

• Drive end-to-end performance tuning, ensuring optimal hardware utilization, software efficiency, and architectural alignment across the ASIC design lifecycle.

You may be a good fit if you have

• Strong understanding of digital design, RTL, and ASIC design flows.

• Hands-on experience with performance verification, simulation, and modeling.

• Comfortable developing checkers, coverage monitors, and testbenches in SystemVerilog.

• Skilled in writing Python scripts for automation, data analysis, and performance modeling.

• Experience building and maintaining performance models for chip subsystems.

• Understanding of memory hierarchies, pipelines, interconnects, and compute accelerators.

• Familiarity with performance bottleneck analysis, compiler optimizations, and workload tuning

• Some exposure to kernel level performance metrics and profiling tools.
  

Benefits

• Medical, dental, and vision packages with generous premium coverage

  • $500 per month credit for waiving medical benefits

• Various wellness benefits covering fitness, mental health, and more

• Daily lunch + dinner in our office

• Unlimited compute budget subject to ROI justification

How we’re different

Etched believes in the Bitter Lesson. We are the first inference-focused frontier AI system, betting early on transformer and transformer-like architectures and on increasing model sizes. Our addressable market is the entirety of inference, unlike many of our competitors.

We are a fully in-person team in San Jose (Santana Row), and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both and work across disciplines as needed.