Design Verification Engineer - Accelerators

Meta; Sunnyvale, San Diego, Redmond, Austin (CA, CA, WA, TX); Sur place; USD 180 000 - 260 000; Plein temps

Résumé du poste

Meta is hiring a Design Verification lead to own verification for complex computer vision and imaging accelerator IP and subsystems. You will define the verification strategy across multiple IPs and build scalable DV infrastructure spanning chips and programs.

The role requires 8+ years in SystemVerilog/UVM/C++, leadership experience, and deep verification expertise across SoC tape-out, formal methods, emulation, or low-power verification.

Qualifications

• 8+ years hands-on verification experience with SystemVerilog, UVM and C/C++ at IP/SoC level.
• Led DV for complex IP or SoC through tape-out and sign-off.
• Defined and ran verification plans, coverage and closure metrics across multiple blocks or IPs.
• Built UVM verification environments and reusable components.
• Experience in formal verification, emulation/FPGA prototyping, or low-power verification.

Responsabilités

• Own verification strategy across multiple IPs and subsystems.
• Build and scale DV infrastructure across chips and programs.
• Mentor engineers and coordinate work across teams.
• Verify computer vision, imaging/ISP, DSP or ML accelerator designs.

Connaissances

SystemVerilog

UVM

C/C++

DV strategy

SVA

Python scripting

team leadership

power/UPF verification

Formation

Bachelor's degree in Computer Science / Electrical Engineering / Computer Engineering

Bachelor's degree in related field or equivalent practical experience

Master's or PhD in EE/CE/CS

Description du poste

The AR glasses Meta is building run on custom silicon that delivers serious compute within a tight power budget. Our silicon team designs that silicon, with breakthrough work in computer vision, machine learning, imaging, and sensing. We're hiring a Design Verification (DV) lead to own verification for complex computer vision and imaging accelerator IP and subsystems. In this role, you'll define the verification strategy across multiple IPs and build DV infrastructure that scales across chips and programs.

• Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience
• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
• 8+ years of hands-on verification experience with SystemVerilog, UVM and C/C++ at the IP, subsystem and SoC level
• Has led DV for complex IP or an SoC through tape-out, including owning sign-off
• Has defined and run verification plans, coverage strategies, and closure metrics (functional and code coverage) across multiple blocks or IPs
• Has built UVM verification environments from scratch and designed reusable verification components
• Deep experience in at least one of: formal verification, SystemVerilog Assertions (SVA), emulation/FPGA prototyping, or low-power (UPF) verification
• Strong scripting skills (Python, TCL, Perl, Shell) for building verification tools and flows
• Has led and mentored engineers and coordinated work across teams
• Has verified power-limited mobile, wearable or AR/VR System-on-Chips (SoCs)
• Has managed EDA vendors or contracted DV teams
• Has verified computer vision, imaging/ISP, DSP or ML accelerator designs
• Master's or PhD in EE/CE/CS
• Has rolled out methodology changes (formal, emulation, portable stimulus, ML/AI-assisted verification) across an org
• Has verified hardware against reference models written in C++ or Python, or co-simulated with firmware or software
• Has scaled DV infrastructure (regression farms, CI for hardware, coverage and triage dashboards) across multiple IPs or programs