ASIC Design Engineer

Infotree Global Solutions

Santa Clara (CA)

On-site

USD 166,000 - 187,000

Full time

14 days+

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Job summary

Infotree Global Solutions seeks an Assistant Delivery Manager to oversee ASIC design tasks, including documentation and collaboration with various engineering teams. This role requires a Bachelor's degree and 5-6+ years of experience in ASIC design, with a focus on RTL and automation. Candidates will be responsible for ensuring high-quality designs, contributing to high-stakes projects in semiconductor manufacturing.

Qualifications

5-6+ years' experience required.
Proven track record of ASIC design on several production tape-outs.
Experience in designing RTL blocks for an SOC.

Responsibilities

Write micro-architecture documentation and design blocks per requirements.
Collaborate with architecture and hardware teams.
Implement automation to increase team efficiency.

Skills

ASIC design

RTL design

Timing analysis

Scripting

Power-saving techniques

Documentation

Team collaboration

Education

Bachelor's degree

Job description

2 days ago Be among the first 25 applicants

Infotree Global Solutions provided pay range

This range is provided by Infotree Global Solutions. Your actual pay will be based on your skills and experience — talk with your recruiter to learn more.

Base pay range

$80.00/hr - $90.00/hr

Direct message the job poster from Infotree Global Solutions

Assistant Delivery Manager at Infotree Global Solutions.

US Citizens and GC holders only

KEY RESPONSIBILITIES:

Write micro-architecture documentation and own major portions of the design and implementation of blocks to meet functional, timing, area, and power requirements.
Collaborate with architecture and hardware teams to understand the requirements.
Work with verification and physical design teams to achieve high quality design and successful tape out.
Design and implement logic functions that enable efficient test and debug.
Participate in silicon bring-up for features owned.
Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features.
Implement automation to increase design team efficiency.

EXPERIENCE:

Required

5-6+ years' experience required
Must have proven track record of ASIC design on several production tape-outs.
Experience in Designing RTL block for an SOC.
Experience in integrating ASIC IP into an SOC.
Experience with synthesis, static timing analysis & optimizations.

Nice-to-have:

Experience writing timing constraints and exceptions.
Experience with automation using scripting techniques such as PERL, Python or Tcl
Experience in Power-saving techniques.
Experience with Arm architecture and APB, AXI, CHI protocols.
Experience with design involving Interconnects.
Ability to develop clear and concise engineering documentation.
Ability to organize and present complex technical information.
Strong verbal and written communication skills

EDUCATION: