Design Verification Engineer

Acceler8 Talent; San Francisco (CA); On-site; USD 200,000 - 320,000; Full time

Job summary

Acceler8 Talent is hiring a Design Verification Engineer for an onsite role in Mountain View, CA. The candidate will own verification methodology from day one and build scalable environments for a new AI compute architecture.

Ideal candidates have 5+ years of experience, strong UVM skills, and familiarity with RTL and system-level debugging on modern SoCs, with exposure to PCIe or DDR interfaces.

Qualifications

• 5+ years of experience in design verification.
• Proven ability to build verification environments and UVM from scratch.
• Strong debugging across RTL and system-level issues.
• Experience with modern SoC architectures, interconnects and verification methodologies.
• Exposure to high-performance compute or AI accelerators/CPUs/GPUs is a plus.

Responsibilities

• Own verification methodology from day one.
• Develop scalable verification environments from scratch.
• Work across block and SoC verification for a new AI compute architecture.

Skills

Verification environments design

UVM from scratch

RTL & system-level debugging

SoC architectures & verification

PCIe / DDR interfaces

HPC AI accelerators / CPUs / GPUs

Tools

UVM

RTL debug tools

Job description

Design Verification Engineer - Mountain View, CA (Onsite)

I'm currently hiring for an early-stage AI infrastructure startup building next-generation AI compute hardware from the silicon up. They're developing a brand-new AI-native compute platform designed to power the next wave of large-scale AI systems, giving engineers the opportunity to work on bleeding-edge architecture alongside some of the industry's top hardware talent.

They're looking for experienced Design Verification Engineers who enjoy building from first principles rather than maintaining existing infrastructure. This is a rare opportunity to own verification methodology from day one, develop scalable verification environments from scratch, and work across block and SoC verification on a completely new AI compute architecture in a highly technical startup environment.

What they're looking for:

• 5+ years experience
• Experience building verification environments and UVM infrastructure from scratch
• Strong debugging skills across RTL and system-level issues
• Experience with modern SoC architectures, interconnects and verification methodologies
• Experience with high-performance compute, AI accelerators, CPUs or GPUs is a strong plus
• Exposure to emulation, post-silicon bring-up or high-speed interfaces such as PCIe or DDR is beneficial

Important details:

• Fully onsite in Mountain View, CA
• $200K-320K base +equity