Design Verification Engineer

AECOM; Cupertino (CA); On-site; USD 143,000 - 215,000; Full time

Job summary

AECOM is seeking a Design Verification Engineer in Cupertino, California. You will be responsible for developing verification plans, running simulations, and ensuring seamless verification flow using hardware description languages like VHDL and Verilog. This role offers competitive pay and a range of benefits, emphasizing the importance of your skills in verification engineering within a dynamic team environment.

Benefits

comprehensive medical and dental coverage

retirement benefits

educational reimbursement

discretionary stock unit awards

discounted products

Qualifications

• Bachelor’s degree or foreign equivalent in engineering or related field.
• Knowledge of Verilog RTL and Design RTL.
• Proficiency in Python for automation tasks.

Responsibilities

• Develop verification plans in coordination with design leads.
• Build and maintain verification test bench components.
• Run simulations and debug design issues.

Skills

Verilog RTL

Python

System Verilog

Object-Oriented Programming

Data structures

C++

Education

Bachelor’s degree in Computer Engineering or Electrical Engineering

Job description

Design Verification Engineer

Cupertino, California, United States

Hardware

Summary

Posted: Jun 05, 2025

Weekly Hours: 40

Role Number: 200607012

Imagine what you can do here. Apple is a place where extraordinary people gather to do their best work. Together we create products and experiences people once couldn’t have imagined, and now, can’t imagine living without. It’s the diversity of those people and their ideas that inspires the innovation that runs through everything we do.

Description

APPLE INC has the following available in Cupertino, California, and various unanticipated locations throughout the USA. Develop verification plans in coordination with design leads and architects. Build and maintain portable verification test bench components and environments. Generate directed and constrained random tests. Run simulations and debug design and environment issues. Create functional coverage points, analyze coverage, and improve the test environment to target coverage holes. Create automated verification flows for block verification. Apply knowledge of hardware description languages (VHDL/Verilog) to verify complex designs. Work with other block, memory subsystem, and core level engineers to ensure seamless verification flow. Use System Verilog and other verification tools to design and verify the graphic processing unit. Create and maintain a testbench environment for hardware designs, including identifying and building a software environment to interface with the design. Develop test plans for cache and memory subsystem designs. Write tests to execute test strategy within the test environment. Analyze test failures and debug hardware issues. Contribute to the team's overall methodology for verifying memory subsystems. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. The base pay range for this role is between $143,100 - $214,500/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and educational reimbursement. This role might also be eligible for bonuses, commissions, or relocation assistance. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.

Minimum Qualifications

• Bachelor’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, or related field.
• Knowledge of Verilog RTL and Design RTL.
• RTL simulation and debugging, including simulating designs and using debugging tools.
• Understanding of computer and processor architecture.
• Proficiency in Python, including automation tasks.
• Object-Oriented Programming and knowledge of System Verilog.
• Data structures and programming, including developing verification infrastructure.
• Knowledge of System Verilog, including testbench infrastructure.
• Knowledge of C++ and modeling infrastructure in C++.

Preferred Qualifications

N/A

Apple is an equal opportunity employer committed to inclusion and diversity. We promote equal opportunity regardless of race, color, religion, sex, sexual orientation, gender identity, national origin, disability, veteran status, or other protected characteristics. Learn more about your EEO rights: https://www.eeoc.gov/sites/default/files/2023-06/22-088_EEOC_KnowYourRights6.12ScreenRdr.pdf.

Apple participates in the E-Verify program where required by law: https://www.apple.com/jobs/pdf/EverifyPosterEnglish.pdf. We are committed to reasonable accommodations for applicants with disabilities. Learn more about our policies. Apple is a drug-free workplace and considers qualified applicants with criminal histories in accordance with applicable law. For San Francisco applicants, review the Fair Chance Ordinance. For Massachusetts, note the law regarding lie detector tests.