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A leading technology company is seeking a Design Verification Engineer to contribute to the development of high-quality technologies. The role involves collaboration with teams on cutting-edge IPs and requires strong analytical skills and attention to detail. Ideal candidates will have a background in ASIC design verification and experience with relevant tools and languages.
We care deeply about transforming lives with AMD technology to enrich our industry, communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences—key for data centers, artificial intelligence, PCs, gaming, and embedded systems. Underpinning our mission is AMD's culture: pushing the limits of innovation to solve important challenges, striving for execution excellence, and fostering a culture of being direct, humble, collaborative, and inclusive of diverse perspectives.
We are seeking an adaptive, self-motivated Design Verification Engineer to join our growing team. As a key contributor, you will help drive and enhance AMD's ability to deliver high-quality, industry-leading technologies. You will work with teams developing leading-edge IPs, RTL, firmware, circuits, and architectures.
You have a passion for modern, complex processor architecture and ASIC/SoC verification. You are a team player with excellent communication skills, experienced in collaborating across different sites and time zones. You possess strong analytical and problem-solving skills, are eager to learn, and ready to tackle challenges. The role involves working closely with senior silicon design and firmware engineers. Attention to detail, accuracy, and good communication are essential.
Santa Clara, CA
#LI-SL3
Details of benefits offered are provided at AMD benefits overview. AMD is an equal opportunity employer, considering all applicants without discrimination based on age, race, gender, disability, or other protected characteristics. We encourage diverse applicants and will provide accommodations during the recruitment process.