Verification Design Engineer

Advanced Micro Devices, Inc.; California, San Jose (MO, CA); Hybrid; USD 90,000 - 150,000; Full time

Job summary

Join a forward-thinking company as a Verification Engineer, where your expertise in digital design and verification will drive innovation. In this role, you'll lead the verification of Network-on-Chip IPs, collaborating with talented engineers across various locations. You'll design efficient testbenches and utilize advanced verification techniques to ensure functional correctness. This is an exciting opportunity to be part of a team that pushes the boundaries of technology, contributing to the development of cutting-edge computing solutions. If you're passionate about complex digital design and eager to tackle challenging problems, this role is for you.

Benefits

Health insurance

Retirement plan

Flexible working hours

Remote work options

Professional development opportunities

Qualifications

• Experience with UVM, OVM, VMM, and System Verilog test benches.
• Strong understanding of verification techniques including assertion and coverage-driven verification.

Responsibilities

• Plan verification of complex digital design blocks and create comprehensive test plans.
• Design and architect testbenches in System Verilog and UVM.

Skills

System Verilog

UVM

Verilog

Debugging

Coverage-driven verification

Analytical skills

Problem-solving

Education

Bachelor's degree in Computer Engineering

Master's degree in Electrical Engineering

Tools

Synopsys VCS

Cadence IES

Formal property checking tools

Job description

WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences - the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world's most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.

AMD together we advance_

THE ROLE:

The verification team at AMD is looking for an experienced Verification Engineer to lead and contribute on the verification of Network on Chip IPs and Subsystems. The individual will help architect, develop and use simulation and/or formal based verification environments, at block and subsystem level, to prove the functional correctness of Network-On-Chip (NOC) IPs, subsystems and SOC designs.

THE PERSON:

You have a passion for modern, complex digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with other engineers located in different sites/time zones. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES:

• Plan verification of complex digital design blocks by fully understanding the architecture and design specifications
• Interact with architects and design engineers to create a comprehensive verification test plan
• Design and architect testbenches in System Verilog and UVM to complete verification of the design in an efficient manner
• Create and enhance constrained-random and/or directed verification environments, and formally verify designs with System Verilog Assertions (SVA) and industry leading formal tools
• Debug tests with design engineers to deliver functionally correct design blocks
• Identify and write coverage measures for stimulus quality improvements
• Perform coverage analysis to identify verification holes and achieve closure on coverage metrics

PREFERRED EXPERIENCE:

• Experienced with development of UVM, OVM, VMM and/or System Verilog, Verilog test benches and usage of simulation tools/debug environments like Synopsys VCS, Cadence IES to test block level/full chip SOCs and FPGAs.
• Strong understanding of state of the art of verification techniques, including assertion and coverage-driven verification.
• Strong understanding of different phases of ASIC and/or full custom chip development is required.
• Experience in block level NOC (Net work on Chip) verification is a plus.
• Verification Experience in protocols like AXI3/4, DDR4/5, HBM, PCIe, Processors, Graphics is a plus.
• Experience as a verification architect, establishing the verification methodology, tools and infrastructure for high performance FPGAs, SOCs and/or VLSI designs is a plus.
• Experience with gate level simulation, power verification, reset verification, contention checking, abstraction techniques is a plus.
• Familiarity with verification management tools as well as understanding of database management particularly as it pertains to regression management is a plus.
• Experience with formal property checking tools such as Cadence (IEV), Jasper and Synopsys (VC-Formal, Magellan) is a plus.
• PCIe protocol experience is a plus

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

LOCATION: San Jose, CA

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Benefits offered are described: AMD benefits at a glance.

AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.